^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Routines for control of MPU-401 in UART mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * MPU-401 supports UART mode which is not capable generate transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * interrupts thus output is done via polling. Without interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * input is done also via polling. Do not expect good performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 13-03-2003:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Added support for different kind of hardware I/O. Build in choices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * are port and mmio. For other kind of I/O, set mpu->read and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * mpu->write to your own I/O functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_DESCRIPTION("Routines for control of MPU-401 in UART mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void snd_mpu401_uart_input_read(struct snd_mpu401 * mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void snd_mpu401_uart_output_write(struct snd_mpu401 * mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define snd_mpu401_input_avail(mpu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (!(mpu->read(mpu, MPU401C(mpu)) & MPU401_RX_EMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define snd_mpu401_output_ready(mpu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (!(mpu->read(mpu, MPU401C(mpu)) & MPU401_TX_FULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Build in lowlevel io */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void mpu401_write_port(struct snd_mpu401 *mpu, unsigned char data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) outb(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned char mpu401_read_port(struct snd_mpu401 *mpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return inb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void mpu401_write_mmio(struct snd_mpu401 *mpu, unsigned char data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writeb(data, (void __iomem *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static unsigned char mpu401_read_mmio(struct snd_mpu401 *mpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return readb((void __iomem *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void snd_mpu401_uart_clear_rx(struct snd_mpu401 *mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) for (; timeout > 0 && snd_mpu401_input_avail(mpu); timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mpu->read(mpu, MPU401D(mpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (timeout <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) snd_printk(KERN_ERR "cmd: clear rx timeout (status = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mpu->read(mpu, MPU401C(mpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void uart_interrupt_tx(struct snd_mpu401 *mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (test_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) test_bit(MPU401_MODE_BIT_OUTPUT_TRIGGER, &mpu->mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) spin_lock_irqsave(&mpu->output_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) snd_mpu401_uart_output_write(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spin_unlock_irqrestore(&mpu->output_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void _snd_mpu401_uart_interrupt(struct snd_mpu401 *mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (mpu->info_flags & MPU401_INFO_INPUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_lock_irqsave(&mpu->input_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (test_bit(MPU401_MODE_BIT_INPUT, &mpu->mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) snd_mpu401_uart_input_read(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) snd_mpu401_uart_clear_rx(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_unlock_irqrestore(&mpu->input_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (! (mpu->info_flags & MPU401_INFO_TX_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* ok. for better Tx performance try do some output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) when input is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) uart_interrupt_tx(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * snd_mpu401_uart_interrupt - generic MPU401-UART interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @irq: the irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @dev_id: mpu401 instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Processes the interrupt for MPU401-UART i/o.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Return: %IRQ_HANDLED if the interrupt was handled. %IRQ_NONE otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) irqreturn_t snd_mpu401_uart_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct snd_mpu401 *mpu = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) _snd_mpu401_uart_interrupt(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) EXPORT_SYMBOL(snd_mpu401_uart_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * snd_mpu401_uart_interrupt_tx - generic MPU401-UART transmit irq handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @irq: the irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @dev_id: mpu401 instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Processes the interrupt for MPU401-UART output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Return: %IRQ_HANDLED if the interrupt was handled. %IRQ_NONE otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) irqreturn_t snd_mpu401_uart_interrupt_tx(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct snd_mpu401 *mpu = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) uart_interrupt_tx(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) EXPORT_SYMBOL(snd_mpu401_uart_interrupt_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * timer callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * reprogram the timer and call the interrupt job
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void snd_mpu401_uart_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct snd_mpu401 *mpu = from_timer(mpu, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spin_lock_irqsave(&mpu->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*mpu->mode |= MPU401_MODE_TIMER;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mod_timer(&mpu->timer, 1 + jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_unlock_irqrestore(&mpu->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (mpu->rmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) _snd_mpu401_uart_interrupt(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * initialize the timer callback if not programmed yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void snd_mpu401_uart_add_timer (struct snd_mpu401 *mpu, int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) spin_lock_irqsave (&mpu->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (mpu->timer_invoked == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) timer_setup(&mpu->timer, snd_mpu401_uart_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mod_timer(&mpu->timer, 1 + jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mpu->timer_invoked |= input ? MPU401_MODE_INPUT_TIMER :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MPU401_MODE_OUTPUT_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_unlock_irqrestore (&mpu->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * remove the timer callback if still active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void snd_mpu401_uart_remove_timer (struct snd_mpu401 *mpu, int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_lock_irqsave (&mpu->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (mpu->timer_invoked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mpu->timer_invoked &= input ? ~MPU401_MODE_INPUT_TIMER :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ~MPU401_MODE_OUTPUT_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (! mpu->timer_invoked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) del_timer(&mpu->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) spin_unlock_irqrestore (&mpu->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * send a UART command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * return zero if successful, non-zero for some errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int snd_mpu401_uart_cmd(struct snd_mpu401 * mpu, unsigned char cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int timeout, ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spin_lock_irqsave(&mpu->input_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (mpu->hardware != MPU401_HW_TRID4DWAVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mpu->write(mpu, 0x00, MPU401D(mpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*snd_mpu401_uart_clear_rx(mpu);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* ok. standard MPU-401 initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (mpu->hardware != MPU401_HW_SB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (timeout = 1000; timeout > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) !snd_mpu401_output_ready(mpu); timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) snd_printk(KERN_ERR "cmd: tx timeout (status = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mpu->read(mpu, MPU401C(mpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mpu->write(mpu, cmd, MPU401C(mpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ack && !(mpu->info_flags & MPU401_INFO_NO_ACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) while (!ok && timeout-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (snd_mpu401_input_avail(mpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (mpu->read(mpu, MPU401D(mpu)) == MPU401_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!ok && mpu->read(mpu, MPU401D(mpu)) == MPU401_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_unlock_irqrestore(&mpu->input_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) snd_printk(KERN_ERR "cmd: 0x%x failed at 0x%lx "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "(status = 0x%x, data = 0x%x)\n", cmd, mpu->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mpu->read(mpu, MPU401C(mpu)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mpu->read(mpu, MPU401D(mpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int snd_mpu401_do_reset(struct snd_mpu401 *mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (snd_mpu401_uart_cmd(mpu, MPU401_RESET, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (snd_mpu401_uart_cmd(mpu, MPU401_ENTER_UART, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * input/output open/close - protected by open_mutex in rawmidi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int snd_mpu401_uart_input_open(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct snd_mpu401 *mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mpu = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (mpu->open_input && (err = mpu->open_input(mpu)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (! test_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (snd_mpu401_do_reset(mpu) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mpu->substream_input = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) set_bit(MPU401_MODE_BIT_INPUT, &mpu->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (mpu->open_input && mpu->close_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mpu->close_input(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int snd_mpu401_uart_output_open(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct snd_mpu401 *mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mpu = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (mpu->open_output && (err = mpu->open_output(mpu)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (! test_bit(MPU401_MODE_BIT_INPUT, &mpu->mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (snd_mpu401_do_reset(mpu) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mpu->substream_output = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) set_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (mpu->open_output && mpu->close_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mpu->close_output(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int snd_mpu401_uart_input_close(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct snd_mpu401 *mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mpu = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clear_bit(MPU401_MODE_BIT_INPUT, &mpu->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mpu->substream_input = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (! test_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) err = snd_mpu401_uart_cmd(mpu, MPU401_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (mpu->close_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mpu->close_input(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int snd_mpu401_uart_output_close(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_mpu401 *mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mpu = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clear_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mpu->substream_output = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (! test_bit(MPU401_MODE_BIT_INPUT, &mpu->mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err = snd_mpu401_uart_cmd(mpu, MPU401_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (mpu->close_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mpu->close_output(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * trigger input callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) snd_mpu401_uart_input_trigger(struct snd_rawmidi_substream *substream, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct snd_mpu401 *mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int max = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mpu = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (! test_and_set_bit(MPU401_MODE_BIT_INPUT_TRIGGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) &mpu->mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* first time - flush FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) while (max-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mpu->read(mpu, MPU401D(mpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (mpu->info_flags & MPU401_INFO_USE_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) snd_mpu401_uart_add_timer(mpu, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* read data in advance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_lock_irqsave(&mpu->input_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) snd_mpu401_uart_input_read(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spin_unlock_irqrestore(&mpu->input_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (mpu->info_flags & MPU401_INFO_USE_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) snd_mpu401_uart_remove_timer(mpu, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) clear_bit(MPU401_MODE_BIT_INPUT_TRIGGER, &mpu->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * transfer input pending data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * call with input_lock spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void snd_mpu401_uart_input_read(struct snd_mpu401 * mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int max = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) while (max-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (! snd_mpu401_input_avail(mpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break; /* input not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) byte = mpu->read(mpu, MPU401D(mpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (test_bit(MPU401_MODE_BIT_INPUT_TRIGGER, &mpu->mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) snd_rawmidi_receive(mpu->substream_input, &byte, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Tx FIFO sizes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * CS4237B - 16 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * AudioDrive ES1688 - 12 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * S3 SonicVibes - 8 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * SoundBlaster AWE 64 - 2 bytes (ugly hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * write output pending bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * call with output_lock spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void snd_mpu401_uart_output_write(struct snd_mpu401 * mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int max = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (snd_rawmidi_transmit_peek(mpu->substream_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &byte, 1) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Try twice because there is hardware that insists on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * setting the output busy bit after each write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!snd_mpu401_output_ready(mpu) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) !snd_mpu401_output_ready(mpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break; /* Tx FIFO full - try again later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mpu->write(mpu, byte, MPU401D(mpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) snd_rawmidi_transmit_ack(mpu->substream_output, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) snd_mpu401_uart_remove_timer (mpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break; /* no other data - leave the tx loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } while (--max > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * output trigger callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) snd_mpu401_uart_output_trigger(struct snd_rawmidi_substream *substream, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct snd_mpu401 *mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mpu = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) set_bit(MPU401_MODE_BIT_OUTPUT_TRIGGER, &mpu->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* try to add the timer at each output trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * since the output timer might have been removed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * snd_mpu401_uart_output_write().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (! (mpu->info_flags & MPU401_INFO_TX_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) snd_mpu401_uart_add_timer(mpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* output pending data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spin_lock_irqsave(&mpu->output_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) snd_mpu401_uart_output_write(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_unlock_irqrestore(&mpu->output_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (! (mpu->info_flags & MPU401_INFO_TX_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) snd_mpu401_uart_remove_timer(mpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) clear_bit(MPU401_MODE_BIT_OUTPUT_TRIGGER, &mpu->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct snd_rawmidi_ops snd_mpu401_uart_output =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .open = snd_mpu401_uart_output_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .close = snd_mpu401_uart_output_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .trigger = snd_mpu401_uart_output_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct snd_rawmidi_ops snd_mpu401_uart_input =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .open = snd_mpu401_uart_input_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .close = snd_mpu401_uart_input_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .trigger = snd_mpu401_uart_input_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void snd_mpu401_uart_free(struct snd_rawmidi *rmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct snd_mpu401 *mpu = rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (mpu->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) free_irq(mpu->irq, (void *) mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) release_and_free_resource(mpu->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) kfree(mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * snd_mpu401_uart_new - create an MPU401-UART instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * @card: the card instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * @device: the device index, zero-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @hardware: the hardware type, MPU401_HW_XXXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * @port: the base address of MPU401 port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * @info_flags: bitflags MPU401_INFO_XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * @irq: the ISA irq number, -1 if not to be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * @rrawmidi: the pointer to store the new rawmidi instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Creates a new MPU-401 instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Note that the rawmidi instance is returned on the rrawmidi argument,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * not the mpu401 instance itself. To access to the mpu401 instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * cast from rawmidi->private_data (with struct snd_mpu401 magic-cast).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Return: Zero if successful, or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int snd_mpu401_uart_new(struct snd_card *card, int device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int info_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct snd_rawmidi ** rrawmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct snd_mpu401 *mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int in_enable, out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (rrawmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *rrawmidi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (! (info_flags & (MPU401_INFO_INPUT | MPU401_INFO_OUTPUT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) info_flags |= MPU401_INFO_INPUT | MPU401_INFO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) in_enable = (info_flags & MPU401_INFO_INPUT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) out_enable = (info_flags & MPU401_INFO_OUTPUT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if ((err = snd_rawmidi_new(card, "MPU-401U", device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) out_enable, in_enable, &rmidi)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mpu = kzalloc(sizeof(*mpu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!mpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rmidi->private_data = mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rmidi->private_free = snd_mpu401_uart_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_lock_init(&mpu->input_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_lock_init(&mpu->output_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spin_lock_init(&mpu->timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mpu->hardware = hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mpu->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (! (info_flags & MPU401_INFO_INTEGRATED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int res_size = hardware == MPU401_HW_PC98II ? 4 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mpu->res = request_region(port, res_size, "MPU401 UART");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!mpu->res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) snd_printk(KERN_ERR "mpu401_uart: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "unable to grab port 0x%lx size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) port, res_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) goto free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (info_flags & MPU401_INFO_MMIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mpu->write = mpu401_write_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mpu->read = mpu401_read_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mpu->write = mpu401_write_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mpu->read = mpu401_read_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mpu->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (hardware == MPU401_HW_PC98II)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mpu->cport = port + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mpu->cport = port + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (request_irq(irq, snd_mpu401_uart_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "MPU401 UART", (void *) mpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) snd_printk(KERN_ERR "mpu401_uart: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "unable to grab IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (irq < 0 && !(info_flags & MPU401_INFO_IRQ_HOOK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) info_flags |= MPU401_INFO_USE_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mpu->info_flags = info_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mpu->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (card->shortname[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) snprintf(rmidi->name, sizeof(rmidi->name), "%s MIDI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) sprintf(rmidi->name, "MPU-401 MIDI %d-%d",card->number, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (out_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) &snd_mpu401_uart_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (in_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) &snd_mpu401_uart_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (out_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) rmidi->info_flags |= SNDRV_RAWMIDI_INFO_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mpu->rmidi = rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (rrawmidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *rrawmidi = rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) free_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) snd_device_free(card, rmidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) EXPORT_SYMBOL(snd_mpu401_uart_new);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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