Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Register definitions for Atmel AC97C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2005-2009 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __SOUND_ATMEL_AC97C_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __SOUND_ATMEL_AC97C_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AC97C_MR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AC97C_ICA		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AC97C_OCA		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AC97C_CARHR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AC97C_CATHR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AC97C_CASR		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AC97C_CAMR		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AC97C_CORHR		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AC97C_COTHR		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AC97C_COSR		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AC97C_COMR		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AC97C_SR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AC97C_IER		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AC97C_IDR		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AC97C_IMR		0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AC97C_VERSION		0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AC97C_CATPR		PDC_TPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AC97C_CATCR		PDC_TCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AC97C_CATNPR		PDC_TNPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AC97C_CATNCR		PDC_TNCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AC97C_CARPR		PDC_RPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AC97C_CARCR		PDC_RCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AC97C_CARNPR		PDC_RNPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AC97C_CARNCR		PDC_RNCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AC97C_PTCR		PDC_PTCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AC97C_MR_ENA		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AC97C_MR_WRST		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AC97C_MR_VRA		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AC97C_CSR_TXRDY		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AC97C_CSR_TXEMPTY	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AC97C_CSR_UNRUN		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AC97C_CSR_RXRDY		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AC97C_CSR_OVRUN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AC97C_CSR_ENDTX		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AC97C_CSR_ENDRX		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AC97C_CMR_SIZE_20	(0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AC97C_CMR_SIZE_18	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AC97C_CMR_SIZE_16	(2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AC97C_CMR_SIZE_10	(3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AC97C_CMR_CEM_LITTLE	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AC97C_CMR_CEM_BIG	(0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AC97C_CMR_CENA		(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AC97C_CMR_DMAEN		(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AC97C_SR_CAEVT		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AC97C_SR_COEVT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AC97C_SR_WKUP		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AC97C_SR_SOF		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AC97C_CH_MASK(slot)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	(0x7 << (3 * (AC97_SLOT_##slot - 3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AC97C_CH_ASSIGN(slot, channel)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	(AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AC97C_CHANNEL_NONE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AC97C_CHANNEL_A		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif /* __SOUND_ATMEL_AC97C_H */