^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Atmel AC97C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2009 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/atmel_pdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/memalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "ac97c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Serialize access to opened variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static DEFINE_MUTEX(opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct atmel_ac97c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u64 cur_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int playback_period, capture_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Serialize access to opened variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_desc *reset_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define get_chip(card) ((struct atmel_ac97c *)(card)->private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ac97c_writel(chip, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __raw_writel((val), (chip)->regs + AC97C_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ac97c_readl(chip, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __raw_readl((chip)->regs + AC97C_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct snd_pcm_hardware atmel_ac97c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .info = (SNDRV_PCM_INFO_MMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) | SNDRV_PCM_INFO_MMAP_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) | SNDRV_PCM_INFO_INTERLEAVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) | SNDRV_PCM_INFO_BLOCK_TRANSFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) | SNDRV_PCM_INFO_JOINT_DUPLEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) | SNDRV_PCM_INFO_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) | SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .formats = (SNDRV_PCM_FMTBIT_S16_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) | SNDRV_PCM_FMTBIT_S16_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .rates = (SNDRV_PCM_RATE_CONTINUOUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .buffer_bytes_max = 2 * 2 * 64 * 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .period_bytes_min = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .period_bytes_max = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .periods_min = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .periods_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int atmel_ac97c_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mutex_lock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) chip->opened++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) runtime->hw = atmel_ac97c_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (chip->cur_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) runtime->hw.rate_min = chip->cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) runtime->hw.rate_max = chip->cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (chip->cur_format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) runtime->hw.formats = pcm_format_to_bits(chip->cur_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mutex_unlock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) chip->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int atmel_ac97c_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mutex_lock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) chip->opened++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) runtime->hw = atmel_ac97c_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (chip->cur_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) runtime->hw.rate_min = chip->cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) runtime->hw.rate_max = chip->cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (chip->cur_format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) runtime->hw.formats = pcm_format_to_bits(chip->cur_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mutex_unlock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) chip->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int atmel_ac97c_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mutex_lock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) chip->opened--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!chip->opened) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) chip->cur_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) chip->cur_format = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mutex_unlock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) chip->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int atmel_ac97c_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mutex_lock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) chip->opened--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!chip->opened) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) chip->cur_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) chip->cur_format = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mutex_unlock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) chip->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int atmel_ac97c_playback_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Set restrictions to params. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mutex_lock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) chip->cur_rate = params_rate(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) chip->cur_format = params_format(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mutex_unlock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Set restrictions to params. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mutex_lock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) chip->cur_rate = params_rate(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chip->cur_format = params_format(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mutex_unlock(&opened_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int block_size = frames_to_bytes(runtime, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long word = ac97c_readl(chip, OCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) chip->playback_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* assign channels to AC97C channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) switch (runtime->channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) | AC97C_CH_ASSIGN(PCM_RIGHT, A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* TODO: support more than two channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ac97c_writel(chip, OCA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* configure sample format and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) word = ac97c_readl(chip, CAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (chip->opened <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (runtime->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case SNDRV_PCM_FORMAT_S16_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) word &= ~(AC97C_CMR_CEM_LITTLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) word = ac97c_readl(chip, OCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ac97c_writel(chip, OCA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Enable underrun interrupt on channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) word |= AC97C_CSR_UNRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ac97c_writel(chip, CAMR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Enable channel A event interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) word = ac97c_readl(chip, IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) word |= AC97C_SR_CAEVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ac97c_writel(chip, IER, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* set variable rate if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (runtime->rate != 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) word = ac97c_readl(chip, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) word |= AC97C_MR_VRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ac97c_writel(chip, MR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) word = ac97c_readl(chip, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) word &= ~(AC97C_MR_VRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ac97c_writel(chip, MR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Initialize and start the PDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(runtime->dma_addr + block_size, chip->regs + ATMEL_PDC_TNPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int block_size = frames_to_bytes(runtime, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned long word = ac97c_readl(chip, ICA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) chip->capture_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* assign channels to AC97C channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (runtime->channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) | AC97C_CH_ASSIGN(PCM_RIGHT, A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* TODO: support more than two channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ac97c_writel(chip, ICA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* configure sample format and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) word = ac97c_readl(chip, CAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (chip->opened <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) switch (runtime->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case SNDRV_PCM_FORMAT_S16_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) word &= ~(AC97C_CMR_CEM_LITTLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) word = ac97c_readl(chip, ICA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ac97c_writel(chip, ICA, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Enable overrun interrupt on channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) word |= AC97C_CSR_OVRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ac97c_writel(chip, CAMR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Enable channel A event interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) word = ac97c_readl(chip, IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) word |= AC97C_SR_CAEVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ac97c_writel(chip, IER, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* set variable rate if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (runtime->rate != 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) word = ac97c_readl(chip, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) word |= AC97C_MR_VRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ac97c_writel(chip, MR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) word = ac97c_readl(chip, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) word &= ~(AC97C_MR_VRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ac97c_writel(chip, MR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Initialize and start the PDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) writel(runtime->dma_addr + block_size, chip->regs + ATMEL_PDC_RNPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long camr, ptcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) camr = ac97c_readl(chip, CAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ptcr = ATMEL_PDC_TXTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ptcr |= ATMEL_PDC_TXTDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (chip->opened <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) camr &= ~AC97C_CMR_CENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ac97c_writel(chip, CAMR, camr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long camr, ptcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) camr = ac97c_readl(chip, CAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ptcr = readl(chip->regs + ATMEL_PDC_PTSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ptcr = ATMEL_PDC_RXTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) camr |= AC97C_CMR_CENA | AC97C_CSR_ENDRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ptcr |= ATMEL_PDC_RXTDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (chip->opened <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) camr &= ~AC97C_CMR_CENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ac97c_writel(chip, CAMR, camr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) atmel_ac97c_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) snd_pcm_uframes_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned long bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) bytes = readl(chip->regs + ATMEL_PDC_TPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) bytes -= runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) frames = bytes_to_frames(runtime, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (frames >= runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) frames -= runtime->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) atmel_ac97c_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) snd_pcm_uframes_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) bytes = readl(chip->regs + ATMEL_PDC_RPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) bytes -= runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) frames = bytes_to_frames(runtime, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (frames >= runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) frames -= runtime->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct snd_pcm_ops atmel_ac97_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .open = atmel_ac97c_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .close = atmel_ac97c_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .hw_params = atmel_ac97c_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .prepare = atmel_ac97c_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .trigger = atmel_ac97c_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .pointer = atmel_ac97c_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const struct snd_pcm_ops atmel_ac97_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .open = atmel_ac97c_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .close = atmel_ac97c_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .hw_params = atmel_ac97c_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .prepare = atmel_ac97c_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .trigger = atmel_ac97c_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .pointer = atmel_ac97c_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct atmel_ac97c *chip = (struct atmel_ac97c *)dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 sr = ac97c_readl(chip, SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u32 casr = ac97c_readl(chip, CASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 cosr = ac97c_readl(chip, COSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 camr = ac97c_readl(chip, CAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (sr & AC97C_SR_CAEVT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int offset, next_period, block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_dbg(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (casr & AC97C_CSR_OVRUN) ? " OVRUN" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) (casr & AC97C_CSR_RXRDY) ? " RXRDY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (casr & AC97C_CSR_UNRUN) ? " UNRUN" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) (casr & AC97C_CSR_TXEMPTY) ? " TXEMPTY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (casr & AC97C_CSR_TXRDY) ? " TXRDY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) !casr ? " NONE" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if ((casr & camr) & AC97C_CSR_ENDTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) runtime = chip->playback_substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) block_size = frames_to_bytes(runtime, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) chip->playback_period++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (chip->playback_period == runtime->periods)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) chip->playback_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) next_period = chip->playback_period + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (next_period == runtime->periods)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) next_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) offset = block_size * next_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) writel(runtime->dma_addr + offset, chip->regs + ATMEL_PDC_TNPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) snd_pcm_period_elapsed(chip->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if ((casr & camr) & AC97C_CSR_ENDRX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) runtime = chip->capture_substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) block_size = frames_to_bytes(runtime, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) chip->capture_period++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (chip->capture_period == runtime->periods)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) chip->capture_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) next_period = chip->capture_period + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (next_period == runtime->periods)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) next_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) offset = block_size * next_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) writel(runtime->dma_addr + offset, chip->regs + ATMEL_PDC_RNPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) snd_pcm_period_elapsed(chip->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (sr & AC97C_SR_COEVT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_info(&chip->pdev->dev, "codec channel event%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (cosr & AC97C_CSR_OVRUN) ? " OVRUN" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) (cosr & AC97C_CSR_RXRDY) ? " RXRDY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) (cosr & AC97C_CSR_TXEMPTY) ? " TXEMPTY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) (cosr & AC97C_CSR_TXRDY) ? " TXRDY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) !cosr ? " NONE" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (retval == IRQ_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(&chip->pdev->dev, "spurious interrupt sr 0x%08x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "casr 0x%08x cosr 0x%08x\n", sr, casr, cosr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct ac97_pcm at91_ac97_pcm_defs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .slots = ((1 << AC97_SLOT_PCM_LEFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) | (1 << AC97_SLOT_PCM_RIGHT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* PCM in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .stream = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .slots = ((1 << AC97_SLOT_PCM_LEFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) | (1 << AC97_SLOT_PCM_RIGHT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Mic in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .stream = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .exclusive = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .r = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .slots = (1<<AC97_SLOT_MIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int atmel_ac97c_pcm_new(struct atmel_ac97c *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct snd_pcm_hardware hw = atmel_ac97c_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) retval = snd_ac97_pcm_assign(chip->ac97_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ARRAY_SIZE(at91_ac97_pcm_defs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) at91_ac97_pcm_defs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) retval = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &atmel_ac97_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &atmel_ac97_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &chip->pdev->dev, hw.periods_min * hw.period_bytes_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hw.buffer_bytes_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int atmel_ac97c_mixer_new(struct atmel_ac97c *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct snd_ac97_template template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) memset(&template, 0, sizeof(template));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) template.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void atmel_ac97c_write(struct snd_ac97 *ac97, unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct atmel_ac97c *chip = get_chip(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned long word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int timeout = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) word = (reg & 0x7f) << 16 | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ac97c_writel(chip, COTHR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_dbg(&chip->pdev->dev, "codec write timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static unsigned short atmel_ac97c_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct atmel_ac97c *chip = get_chip(ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned long word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int timeout = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int write = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) word = (0x80 | (reg & 0x7f)) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ac97c_readl(chip, CORHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) retry_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) timeout = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ac97c_writel(chip, COTHR, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto read_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!--write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto timed_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) goto retry_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) read_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned short val = ac97c_readl(chip, CORHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (!--write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) goto timed_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto retry_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) timed_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_dbg(&chip->pdev->dev, "codec read timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static void atmel_ac97c_reset(struct atmel_ac97c *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ac97c_writel(chip, MR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ac97c_writel(chip, MR, AC97C_MR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ac97c_writel(chip, CAMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ac97c_writel(chip, COMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!IS_ERR(chip->reset_pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) gpiod_set_value(chip->reset_pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* AC97 v2.2 specifications says minimum 1 us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) gpiod_set_value(chip->reset_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ac97c_writel(chip, MR, AC97C_MR_WRST | AC97C_MR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ac97c_writel(chip, MR, AC97C_MR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const struct of_device_id atmel_ac97c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { .compatible = "atmel,at91sam9263-ac97c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MODULE_DEVICE_TABLE(of, atmel_ac97c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int atmel_ac97c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct atmel_ac97c *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .write = atmel_ac97c_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .read = atmel_ac97c_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_dbg(&pdev->dev, "no memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_dbg(&pdev->dev, "could not get irq: %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pclk = clk_get(&pdev->dev, "ac97_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (IS_ERR(pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_dbg(&pdev->dev, "no peripheral clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return PTR_ERR(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) retval = clk_prepare_enable(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto err_prepare_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) retval = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) SNDRV_DEFAULT_STR1, THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) sizeof(struct atmel_ac97c), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_dbg(&pdev->dev, "could not create sound card device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) goto err_snd_card_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) chip = get_chip(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) retval = request_irq(irq, atmel_ac97c_interrupt, 0, "AC97C", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(&pdev->dev, "unable to request irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) goto err_request_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) chip->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) strcpy(card->driver, "Atmel AC97C");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) strcpy(card->shortname, "Atmel AC97C");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) sprintf(card->longname, "Atmel AC97 controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) chip->pclk = pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) chip->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) chip->regs = ioremap(regs->start, resource_size(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!chip->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_dbg(&pdev->dev, "could not remap register memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) chip->reset_pin = devm_gpiod_get_index(dev, "ac97", 2, GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (IS_ERR(chip->reset_pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev_dbg(dev, "reset pin not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) atmel_ac97c_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Enable overrun interrupt from codec channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ac97c_writel(chip, COMR, AC97C_CSR_OVRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ac97c_writel(chip, IER, ac97c_readl(chip, IMR) | AC97C_SR_COEVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) retval = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_dbg(&pdev->dev, "could not register on ac97 bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) goto err_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) retval = atmel_ac97c_mixer_new(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_dbg(&pdev->dev, "could not register ac97 mixer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) goto err_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) retval = atmel_ac97c_pcm_new(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_dbg(&pdev->dev, "could not register ac97 pcm device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) goto err_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) retval = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev_dbg(&pdev->dev, "could not register sound card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) goto err_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) platform_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev_info(&pdev->dev, "Atmel AC97 controller at 0x%p, irq = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) chip->regs, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) err_ac97_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) iounmap(chip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) free_irq(irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) err_request_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) err_snd_card_new:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) clk_disable_unprepare(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) err_prepare_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) clk_put(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int atmel_ac97c_suspend(struct device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct snd_card *card = dev_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct atmel_ac97c *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) clk_disable_unprepare(chip->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int atmel_ac97c_resume(struct device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct snd_card *card = dev_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct atmel_ac97c *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int ret = clk_prepare_enable(chip->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static SIMPLE_DEV_PM_OPS(atmel_ac97c_pm, atmel_ac97c_suspend, atmel_ac97c_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define ATMEL_AC97C_PM_OPS &atmel_ac97c_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define ATMEL_AC97C_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int atmel_ac97c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct snd_card *card = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct atmel_ac97c *chip = get_chip(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ac97c_writel(chip, CAMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ac97c_writel(chip, COMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ac97c_writel(chip, MR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) clk_disable_unprepare(chip->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) clk_put(chip->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) iounmap(chip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static struct platform_driver atmel_ac97c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .probe = atmel_ac97c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .remove = atmel_ac97c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "atmel_ac97c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .pm = ATMEL_AC97C_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .of_match_table = atmel_ac97c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) module_platform_driver(atmel_ac97c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MODULE_DESCRIPTION("Driver for Atmel AC97 controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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