^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * which contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Created: Dec 02, 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright: MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pxa2xx-lib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <mach/regs-ac97.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <mach/audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static DEFINE_MUTEX(car_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static volatile long gsr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct clk *ac97_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct clk *ac97conf_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Beware PXA27x bugs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * o Slot 12 read from modem space will hang controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * o CDONE, SDONE interrupt fails after any slot 12 IO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * We therefore have an hybrid approach for waiting on SDONE (interrupt or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 1 jiffy timeout if interrupt never comes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int pxa2xx_ac97_read(int slot, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int val = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) volatile u32 *reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (slot > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mutex_lock(&car_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* set up primary or secondary codec space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg_addr += (reg >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* start read access across the ac97 link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GSR = GSR_CDONE | GSR_SDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val = (*reg_addr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (reg == AC97_GPIO_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) !((GSR | gsr_bits) & GSR_SDONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __func__, reg, GSR | gsr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* valid data now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GSR = GSR_CDONE | GSR_SDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val = (*reg_addr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* but we've just started another cycle... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) out: mutex_unlock(&car_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) volatile u32 *reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mutex_lock(&car_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* set up primary or secondary codec space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg_addr += (reg >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GSR = GSR_CDONE | GSR_SDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *reg_addr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) !((GSR | gsr_bits) & GSR_CDONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __func__, reg, GSR | gsr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mutex_unlock(&car_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #ifdef CONFIG_PXA25x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void pxa_ac97_warm_pxa25x(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GCR |= GCR_WARM_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline void pxa_ac97_cold_pxa25x(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GCR &= GCR_COLD_RST; /* clear everything but nCRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) GCR &= ~GCR_COLD_RST; /* then assert nCRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GCR = GCR_COLD_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_PXA27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline void pxa_ac97_warm_pxa27x(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* warm reset broken on Bulverde, so manually keep AC97 reset high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pxa27x_configure_ac97reset(reset_gpio, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) GCR |= GCR_WARM_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pxa27x_configure_ac97reset(reset_gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline void pxa_ac97_cold_pxa27x(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) GCR &= GCR_COLD_RST; /* clear everything but nCRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) GCR &= ~GCR_COLD_RST; /* then assert nCRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* PXA27x Developers Manual section 13.5.2.2.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk_prepare_enable(ac97conf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk_disable_unprepare(ac97conf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GCR = GCR_COLD_RST | GCR_WARM_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline void pxa_ac97_warm_pxa3xx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Can't use interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) GCR |= GCR_WARM_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline void pxa_ac97_cold_pxa3xx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Hold CLKBPB for 100us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) GCR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GCR = GCR_CLKBPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) GCR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GCR &= GCR_COLD_RST; /* clear everything but nCRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GCR &= ~GCR_COLD_RST; /* then assert nCRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) gsr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Can't use interrupts on PXA3xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GCR = GCR_WARM_RST | GCR_COLD_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool pxa2xx_ac97_try_warm_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long gsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_PXA25x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (cpu_is_pxa25x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pxa_ac97_warm_pxa25x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #ifdef CONFIG_PXA27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pxa_ac97_warm_pxa27x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef CONFIG_PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (cpu_is_pxa3xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pxa_ac97_warm_pxa3xx();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) gsr = GSR | gsr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!(gsr & (GSR_PCR | GSR_SCR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __func__, gsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bool pxa2xx_ac97_try_cold_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long gsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #ifdef CONFIG_PXA25x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (cpu_is_pxa25x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pxa_ac97_cold_pxa25x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef CONFIG_PXA27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pxa_ac97_cold_pxa27x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef CONFIG_PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (cpu_is_pxa3xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pxa_ac97_cold_pxa3xx();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) gsr = GSR | gsr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!(gsr & (GSR_PCR | GSR_SCR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __func__, gsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void pxa2xx_ac97_finish_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) status = GSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GSR = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) gsr_bits |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) wake_up(&gsr_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Although we don't use those we still need to clear them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) since they tend to spuriously trigger when MMC is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (hardware bug? go figure)... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (cpu_is_pxa27x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MISR = MISR_EOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PISR = PISR_EOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MCSR = MCSR_EOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int pxa2xx_ac97_hw_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) GCR |= GCR_ACLINK_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk_disable_unprepare(ac97_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int pxa2xx_ac97_hw_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) clk_prepare_enable(ac97_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int pxa2xx_ac97_hw_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) switch (pdata->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case 95:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case 113:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) reset_gpio = pdata->reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reset_gpio = 113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case -1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(&dev->dev, "Invalid reset GPIO %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pdata->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else if (!pdata && dev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "reset-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (pdata->reset_gpio == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pdata->reset_gpio = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else if (pdata->reset_gpio < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return pdata->reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reset_gpio = pdata->reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reset_gpio = 113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (cpu_is_pxa27x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * This gpio is needed for a work-around to a bug in the ac97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * controller during warm reset. The direction and level is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * here so that it is an output driven high when switching from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * AC97_nRESET alt function to generic gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "pxa27x ac97 reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_err("%s: gpio_request_one() failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto err_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pxa27x_configure_ac97reset(reset_gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (IS_ERR(ac97conf_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = PTR_ERR(ac97conf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ac97conf_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto err_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ac97_clk = clk_get(&dev->dev, "AC97CLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (IS_ERR(ac97_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = PTR_ERR(ac97_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ac97_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = clk_prepare_enable(ac97_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto err_clk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) GCR |= GCR_ACLINK_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err_clk2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk_put(ac97_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ac97_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ac97conf_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk_put(ac97conf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ac97conf_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) err_conf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void pxa2xx_ac97_hw_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gpio_free(reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GCR |= GCR_ACLINK_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) free_irq(IRQ_AC97, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ac97conf_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk_put(ac97conf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ac97conf_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk_disable_unprepare(ac97_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk_put(ac97_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ac97_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_AUTHOR("Nicolas Pitre");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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