^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef AACI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define AACI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Control and status register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * P39.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AACI_CSCH1 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AACI_CSCH2 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AACI_CSCH3 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AACI_CSCH4 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AACI_SR 0x008 /* 12 bits Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AACI_ISR 0x00c /* 7 bits Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AACI_IE 0x010 /* 7 bits Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Other registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AACI_SL1RX 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AACI_SL1TX 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AACI_SL2RX 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AACI_SL2TX 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AACI_SL12RX 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AACI_SL12TX 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AACI_SLFR 0x068 /* slot flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AACI_SLISTAT 0x06c /* slot interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AACI_SLIEN 0x070 /* slot interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AACI_INTCLR 0x074 /* interrupt clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AACI_MAINCR 0x078 /* main control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AACI_RESET 0x07c /* reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AACI_SYNC 0x080 /* sync control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AACI_MAINFR 0x088 /* main flag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AACI_DR1 0x090 /* data read/written fifo 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AACI_DR2 0x0b0 /* data read/written fifo 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AACI_DR3 0x0d0 /* data read/written fifo 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AACI_DR4 0x0f0 /* data read/written fifo 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * TX/RX fifo control register (CR). P48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CR_FEN (1 << 16) /* fifo enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CR_COMPACT (1 << 15) /* compact mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CR_SZ16 (0 << 13) /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CR_SZ18 (1 << 13) /* 18 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CR_SZ20 (2 << 13) /* 20 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CR_SZ12 (3 << 13) /* 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CR_SL12 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CR_SL11 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CR_SL10 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CR_SL9 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CR_SL8 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CR_SL7 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CR_SL6 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CR_SL5 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CR_SL4 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CR_SL3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CR_SL2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CR_SL1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CR_EN (1 << 0) /* transmit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * status register bits. P49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SR_TXU (1 << 9) /* tx underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SR_RXO (1 << 8) /* rx overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SR_TXB (1 << 7) /* tx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SR_RXB (1 << 6) /* rx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SR_TXFF (1 << 5) /* tx fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SR_RXFF (1 << 4) /* rx fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SR_TXHE (1 << 3) /* tx fifo half empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SR_RXHF (1 << 2) /* rx fifo half full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SR_TXFE (1 << 1) /* tx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SR_RXFE (1 << 0) /* rx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * interrupt status register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ISR_URINTR (1 << 5) /* tx underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ISR_ORINTR (1 << 4) /* rx overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ISR_RXINTR (1 << 3) /* rx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ISR_TXINTR (1 << 2) /* tx fifo intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ISR_RXTOINTR (1 << 1) /* tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ISR_TXCINTR (1 << 0) /* tx complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * interrupt enable register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IE_RXTOIE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IE_URIE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IE_ORIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IE_RXIE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IE_TXIE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IE_RXTIE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IE_TXCIE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * interrupt status. P51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ISR_UR (1 << 5) /* tx fifo underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ISR_OR (1 << 4) /* rx fifo overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ISR_RX (1 << 3) /* rx interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ISR_TX (1 << 2) /* tx interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ISR_RXTO (1 << 1) /* rx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ISR_TXC (1 << 0) /* tx complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * interrupt enable. P52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IE_UR (1 << 5) /* tx fifo underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IE_OR (1 << 4) /* rx fifo overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IE_RX (1 << 3) /* rx interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IE_TX (1 << 2) /* tx interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IE_RXTO (1 << 1) /* rx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IE_TXC (1 << 0) /* tx complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * slot flag register bits. P56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SLFR_12TXE (1 << 11) /* slot 12 tx empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SLFR_12RXV (1 << 10) /* slot 12 rx valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SLFR_2TXE (1 << 9) /* slot 2 tx empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SLFR_2RXV (1 << 8) /* slot 2 rx valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SLFR_1TXE (1 << 7) /* slot 1 tx empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SLFR_1RXV (1 << 6) /* slot 1 rx valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SLFR_12TXB (1 << 5) /* slot 12 tx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SLFR_12RXB (1 << 4) /* slot 12 rx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SLFR_2TXB (1 << 3) /* slot 2 tx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SLFR_2RXB (1 << 2) /* slot 2 rx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SLFR_1TXB (1 << 1) /* slot 1 tx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SLFR_1RXB (1 << 0) /* slot 1 rx busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Interrupt clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ICLR_RXTOFEC4 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ICLR_RXTOFEC3 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ICLR_RXTOFEC2 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ICLR_RXTOFEC1 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ICLR_TXUEC4 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ICLR_TXUEC3 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ICLR_TXUEC2 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ICLR_TXUEC1 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ICLR_RXOEC4 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ICLR_RXOEC3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ICLR_RXOEC2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ICLR_RXOEC1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ICLR_WISC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Main control register bits. P62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MAINCR_DMAEN (1 << 9) /* dma enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MAINCR_LPM (1 << 2) /* low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MAINCR_LOOPBK (1 << 1) /* loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MAINCR_IE (1 << 0) /* aaci interface enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Reset register bits. P65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RESET_NRST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Sync register bits. P65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SYNC_FORCE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Main flag register bits. P66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MAINFR_TXB (1 << 1) /* transmit busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MAINFR_RXB (1 << 0) /* receive busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct aaci_runtime {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __iomem *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct ac97_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int pcm_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int period; /* byte size of a "period" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * PIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int fifo_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct aaci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct amba_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct mutex irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* AC'97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct mutex ac97_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 maincr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct aaci_runtime playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct aaci_runtime capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ACSTREAM_FRONT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ACSTREAM_SURROUND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ACSTREAM_LFE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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