^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i2sbus driver -- interface register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __I2SBUS_INTERFACE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __I2SBUS_INTERFACE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* i2s bus control registers, at least what we know about them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __PAD(m,n) u8 __pad##m[n]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _PAD(line, n) __PAD(line, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PAD(n) _PAD(__LINE__, (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct i2s_interface_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __le32 intr_ctl; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) __le32 serial_format; /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __le32 codec_msg_out; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) __le32 codec_msg_in; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __le32 frame_count; /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __le32 frame_match; /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __le32 data_word_sizes; /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __le32 peak_level_sel; /* 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __le32 peak_level_in0; /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __le32 peak_level_in1; /* 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PAD(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* total size: 0x100 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) } __attribute__((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* interrupt register is just a bitfield with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * interrupt enable and pending bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2S_REG_INTR_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define I2S_INT_FRAME_COUNT (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define I2S_PENDING_FRAME_COUNT (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define I2S_INT_MESSAGE_FLAG (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define I2S_PENDING_MESSAGE_FLAG (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # define I2S_INT_NEW_PEAK (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) # define I2S_PENDING_NEW_PEAK (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define I2S_INT_CLOCKS_STOPPED (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define I2S_PENDING_CLOCKS_STOPPED (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) # define I2S_INT_EXTERNAL_SYNC_ERROR (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define I2S_PENDING_EXTERNAL_SYNC_ERROR (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define I2S_INT_EXTERNAL_SYNC_OK (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define I2S_PENDING_EXTERNAL_SYNC_OK (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define I2S_INT_NEW_SAMPLE_RATE (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define I2S_PENDING_NEW_SAMPLE_RATE (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define I2S_INT_STATUS_FLAG (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define I2S_PENDING_STATUS_FLAG (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* serial format register is more interesting :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * It contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * - clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * - MClk divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * - SClk divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * - SClk master flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * - external sample frequency interrupt (don't understand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * - external sample frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2S_REG_SERIAL_FORMAT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define I2S_SF_CLOCK_SOURCE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define I2S_SF_CLOCK_SOURCE_MASK (3<<I2S_SF_CLOCK_SOURCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define I2S_SF_CLOCK_SOURCE_18MHz (0<<I2S_SF_CLOCK_SOURCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define I2S_SF_CLOCK_SOURCE_45MHz (1<<I2S_SF_CLOCK_SOURCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define I2S_SF_CLOCK_SOURCE_49MHz (2<<I2S_SF_CLOCK_SOURCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* also, let's define the exact clock speeds here, in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2S_CLOCK_SPEED_18MHz 18432000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2S_CLOCK_SPEED_45MHz 45158400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2S_CLOCK_SPEED_49MHz 49152000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* MClk is the clock that drives the codec, usually called its 'system clock'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * It is derived by taking only every 'divisor' tick of the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) # define I2S_SF_MCLKDIV_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define I2S_SF_MCLKDIV_MASK (0x1F<<I2S_SF_MCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define I2S_SF_MCLKDIV_1 (0x14<<I2S_SF_MCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define I2S_SF_MCLKDIV_3 (0x13<<I2S_SF_MCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define I2S_SF_MCLKDIV_5 (0x12<<I2S_SF_MCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define I2S_SF_MCLKDIV_14 (0x0E<<I2S_SF_MCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline int i2s_sf_mclkdiv(int div, int *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch(div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 1: *out |= I2S_SF_MCLKDIV_1; return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case 3: *out |= I2S_SF_MCLKDIV_3; return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 5: *out |= I2S_SF_MCLKDIV_5; return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 14: *out |= I2S_SF_MCLKDIV_14; return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (div%2) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) d = div/2-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (d == 0x14 || d == 0x13 || d == 0x12 || d == 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *out |= I2S_SF_MCLKDIV_OTHER(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* SClk is the clock that drives the i2s wire bus. Note that it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * derived from the MClk above by taking only every 'divisor' tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * of MClk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define I2S_SF_SCLKDIV_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define I2S_SF_SCLKDIV_MASK (0xF<<I2S_SF_SCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define I2S_SF_SCLKDIV_1 (8<<I2S_SF_SCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define I2S_SF_SCLKDIV_3 (9<<I2S_SF_SCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline int i2s_sf_sclkdiv(int div, int *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch(div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 1: *out |= I2S_SF_SCLKDIV_1; return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 3: *out |= I2S_SF_SCLKDIV_3; return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (div%2) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) d = div/2-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (d == 8 || d == 9) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *out |= I2S_SF_SCLKDIV_OTHER(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define I2S_SF_SCLK_MASTER (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* serial format is the way the data is put to the i2s wire bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define I2S_SF_SERIAL_FORMAT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define I2S_SF_SERIAL_FORMAT_MASK (7<<I2S_SF_SERIAL_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define I2S_SF_SERIAL_FORMAT_SONY (0<<I2S_SF_SERIAL_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define I2S_SF_SERIAL_FORMAT_I2S_64X (1<<I2S_SF_SERIAL_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define I2S_SF_SERIAL_FORMAT_I2S_32X (2<<I2S_SF_SERIAL_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define I2S_SF_SERIAL_FORMAT_I2S_DAV (4<<I2S_SF_SERIAL_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define I2S_SF_SERIAL_FORMAT_I2S_SILABS (5<<I2S_SF_SERIAL_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define I2S_SF_EXT_SAMPLE_FREQ_INT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define I2S_SF_EXT_SAMPLE_FREQ_INT_MASK (0xF<<I2S_SF_SAMPLE_FREQ_INT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* probably gives external frequency? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define I2S_SF_EXT_SAMPLE_FREQ_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* used to send codec messages, but how isn't clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define I2S_REG_CODEC_MSG_OUT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* used to receive codec messages, but how isn't clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define I2S_REG_CODEC_MSG_IN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* frame count reg isn't clear to me yet, but probably useful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define I2S_REG_FRAME_COUNT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* program to some value, and get interrupt if frame count reaches it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define I2S_REG_FRAME_MATCH 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* this register describes how the bus transfers data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define I2S_REG_DATA_WORD_SIZES 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* number of interleaved input channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) # define I2S_DWS_NUM_CHANNELS_IN_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define I2S_DWS_NUM_CHANNELS_IN_MASK (0x1F<<I2S_DWS_NUM_CHANNELS_IN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* word size of input data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) # define I2S_DWS_DATA_IN_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) # define I2S_DWS_DATA_IN_16BIT (0<<I2S_DWS_DATA_IN_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define I2S_DWS_DATA_IN_24BIT (3<<I2S_DWS_DATA_IN_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* number of interleaved output channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define I2S_DWS_NUM_CHANNELS_OUT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) # define I2S_DWS_NUM_CHANNELS_OUT_MASK (0x1F<<I2S_DWS_NUM_CHANNELS_OUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* word size of output data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) # define I2S_DWS_DATA_OUT_SIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define I2S_DWS_DATA_OUT_16BIT (0<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define I2S_DWS_DATA_OUT_24BIT (3<<I2S_DWS_DATA_OUT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define I2S_REG_PEAK_LEVEL_SEL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define I2S_REG_PEAK_LEVEL_IN0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define I2S_REG_PEAK_LEVEL_IN1 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif /* __I2SBUS_INTERFACE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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