Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Apple Onboard Audio driver for Onyx codec (header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __SND_AOA_CODEC_ONYX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __SND_AOA_CODEC_ONYX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/pmac_low_i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* PCM3052 register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* the attenuation registers take values from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * -1 (0dB) to -127 (-63.0 dB) or others (muted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ONYX_REG_DAC_ATTEN_LEFT		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FIRSTREGISTER			ONYX_REG_DAC_ATTEN_LEFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ONYX_REG_DAC_ATTEN_RIGHT	66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ONYX_REG_CONTROL		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #	define ONYX_MRST		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #	define ONYX_SRST		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #	define ONYX_ADPSV		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #	define ONYX_DAPSV		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #	define ONYX_SILICONVERSION	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* all others reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ONYX_REG_DAC_CONTROL		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #	define ONYX_OVR1		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #	define ONYX_MUTE_RIGHT		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #	define ONYX_MUTE_LEFT		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ONYX_REG_DAC_DEEMPH		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #	define ONYX_DIGDEEMPH_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #	define ONYX_DIGDEEMPH_MASK	(3<<ONYX_DIGDEEMPH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #	define ONYX_DIGDEEMPH_CTRL	(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ONYX_REG_DAC_FILTER		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #	define ONYX_ROLLOFF_FAST	(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #	define ONYX_DAC_FILTER_ALWAYS	(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define	ONYX_REG_DAC_OUTPHASE		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #	define ONYX_OUTPHASE_INVERTED	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ONYX_REG_ADC_CONTROL		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #	define ONYX_ADC_INPUT_MIC	(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* 8 + input gain in dB, valid range for input gain is -4 .. 20 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #	define ONYX_ADC_PGA_GAIN_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ONYX_REG_ADC_HPF_BYPASS		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #	define ONYX_HPF_DISABLE		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #	define ONYX_ADC_HPF_ALWAYS	(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ONYX_REG_DIG_INFO1		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #	define ONYX_MASK_DIN_TO_BPZ	(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* bits 1-5 control channel bits 1-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #	define ONYX_DIGOUT_DISABLE	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ONYX_REG_DIG_INFO2		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* controls channel bits 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ONYX_REG_DIG_INFO3		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* control channel bits 24-29, high 2 bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ONYX_REG_DIG_INFO4		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #	define ONYX_VALIDL		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #	define ONYX_VALIDR		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #	define ONYX_SPDIF_ENABLE	(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* lower 4 bits control bits 32-35 of channel control and word length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #	define ONYX_WORDLEN_MASK	(0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif /* __SND_AOA_CODEC_ONYX_H */