^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Mediated virtual PCI serial host device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Neo Jia <cjia@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Kirti Wankhede <kwankhede@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Sample driver that creates mdev device that simulates serial port over PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/cdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/uuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/vfio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <uapi/linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/eventfd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * #defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VERSION_STRING "0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRIVER_AUTHOR "NVIDIA Corporation"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MTTY_CLASS_NAME "mtty"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MTTY_NAME "mtty"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MTTY_STRING_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MTTY_CONFIG_SPACE_SIZE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MTTY_IO_BAR_SIZE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MTTY_MMIO_BAR_SIZE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STORE_LE16(addr, val) (*(u16 *)addr = val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STORE_LE32(addr, val) (*(u32 *)addr = val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CIRCULAR_BUF_INC_IDX(idx) (idx = (idx + 1) & (MAX_FIFO_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MTTY_VFIO_PCI_OFFSET_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MTTY_VFIO_PCI_OFFSET_TO_INDEX(off) (off >> MTTY_VFIO_PCI_OFFSET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MTTY_VFIO_PCI_INDEX_TO_OFFSET(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ((u64)(index) << MTTY_VFIO_PCI_OFFSET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MTTY_VFIO_PCI_OFFSET_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (((u64)(1) << MTTY_VFIO_PCI_OFFSET_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAX_MTTYS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Global Structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct mtty_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_t vd_devt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct class *vd_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct cdev vd_cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct idr vd_idr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } mtty_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct mdev_region_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u64 phys_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u64 vfio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #if defined(DEBUG_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char *wr_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "IER",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "FCR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "LCR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "MCR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "LSR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "MSR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "SCR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char *rd_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "IER",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "IIR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "LCR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "MCR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "LSR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "MSR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "SCR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* loop back buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct rxtx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 fifo[MAX_FIFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 head, tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct serial_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 uart_reg[8]; /* 8 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct rxtx rxtx; /* loop back buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool dlab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bool overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 fcr; /* FIFO control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 max_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 intr_trigger_level; /* interrupt trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* State of each mdev device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mdev_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int irq_fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct eventfd_ctx *intx_evtfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct eventfd_ctx *msi_evtfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int irq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 *vconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mutex ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mdev_device *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 bar_mask[VFIO_PCI_NUM_REGIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct list_head next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct serial_port s[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mutex rxtx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct vfio_device_info dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct mutex mdev_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct list_head mdev_devices_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct file_operations vd_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* function prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int mtty_trigger_interrupt(struct mdev_state *mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Helper functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void dump_buffer(u8 *buf, uint32_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #if defined(DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pr_info("Buffer:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pr_info("%2x ", *(buf + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if ((i + 1) % 16 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void mtty_create_config_space(struct mdev_state *mdev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* PCI dev ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) STORE_LE32((u32 *) &mdev_state->vconfig[0x0], 0x32534348);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Control: I/O+, Mem-, BusMaster- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) STORE_LE16((u16 *) &mdev_state->vconfig[0x4], 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Status: capabilities list absent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) STORE_LE16((u16 *) &mdev_state->vconfig[0x6], 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Rev ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mdev_state->vconfig[0x8] = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* programming interface class : 16550-compatible serial controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mdev_state->vconfig[0x9] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Sub class : 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mdev_state->vconfig[0xa] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Base class : Simple Communication controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mdev_state->vconfig[0xb] = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* base address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* BAR0: IO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) STORE_LE32((u32 *) &mdev_state->vconfig[0x10], 0x000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mdev_state->bar_mask[0] = ~(MTTY_IO_BAR_SIZE) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (mdev_state->nr_ports == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* BAR1: IO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) STORE_LE32((u32 *) &mdev_state->vconfig[0x14], 0x000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mdev_state->bar_mask[1] = ~(MTTY_IO_BAR_SIZE) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Subsystem ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) STORE_LE32((u32 *) &mdev_state->vconfig[0x2c], 0x32534348);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mdev_state->vconfig[0x34] = 0x00; /* Cap Ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mdev_state->vconfig[0x3d] = 0x01; /* interrupt pin (INTA#) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Vendor specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mdev_state->vconfig[0x40] = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mdev_state->vconfig[0x43] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mdev_state->vconfig[0x44] = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mdev_state->vconfig[0x48] = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mdev_state->vconfig[0x4c] = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mdev_state->vconfig[0x60] = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mdev_state->vconfig[0x61] = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mdev_state->vconfig[0x62] = 0x49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mdev_state->vconfig[0x63] = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mdev_state->vconfig[0x64] = 0x53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mdev_state->vconfig[0x65] = 0x65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mdev_state->vconfig[0x66] = 0x72;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mdev_state->vconfig[0x67] = 0x69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mdev_state->vconfig[0x68] = 0x61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mdev_state->vconfig[0x69] = 0x6c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mdev_state->vconfig[0x6a] = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mdev_state->vconfig[0x6b] = 0x55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mdev_state->vconfig[0x6c] = 0x41;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mdev_state->vconfig[0x6d] = 0x52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mdev_state->vconfig[0x6e] = 0x54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 *buf, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 cfg_addr, bar_mask, bar_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case 0x04: /* device control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case 0x06: /* device status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 0x3c: /* interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mdev_state->vconfig[0x3c] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case 0x3d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Interrupt Pin is hardwired to INTA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * This field is write protected by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 0x10: /* BAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 0x14: /* BAR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (offset == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bar_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else if (offset == 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bar_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if ((mdev_state->nr_ports == 1) && (bar_index == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) STORE_LE32(&mdev_state->vconfig[offset], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cfg_addr = *(u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pr_info("BAR%d addr 0x%x\n", bar_index, cfg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (cfg_addr == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) bar_mask = mdev_state->bar_mask[bar_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cfg_addr = (cfg_addr & bar_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cfg_addr |= (mdev_state->vconfig[offset] & 0x3ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case 0x18: /* BAR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case 0x1c: /* BAR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case 0x20: /* BAR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) STORE_LE32(&mdev_state->vconfig[offset], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pr_info("PCI config write @0x%x of %d bytes not handled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) offset, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u16 offset, u8 *buf, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 data = *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Handle data written by guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case UART_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* if DLAB set, data is LSB of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (mdev_state->s[index].dlab) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mdev_state->s[index].divisor |= data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mutex_lock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* save in TX buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (mdev_state->s[index].rxtx.count <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mdev_state->s[index].max_fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mdev_state->s[index].rxtx.fifo[
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mdev_state->s[index].rxtx.head] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mdev_state->s[index].rxtx.count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mdev_state->s[index].overrun = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Trigger interrupt if receive data interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * enabled and fifo reached trigger level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if ((mdev_state->s[index].uart_reg[UART_IER] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) UART_IER_RDI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (mdev_state->s[index].rxtx.count ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mdev_state->s[index].intr_trigger_level)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* trigger interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #if defined(DEBUG_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pr_err("Serial port %d: Fifo level trigger\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mtty_trigger_interrupt(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #if defined(DEBUG_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pr_err("Serial port %d: Buffer Overflow\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mdev_state->s[index].overrun = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Trigger interrupt if receiver line status interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (mdev_state->s[index].uart_reg[UART_IER] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) UART_IER_RLSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mtty_trigger_interrupt(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mutex_unlock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case UART_IER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* if DLAB set, data is MSB of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (mdev_state->s[index].dlab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mdev_state->s[index].divisor |= (u16)data << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mdev_state->s[index].uart_reg[offset] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mutex_lock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if ((data & UART_IER_THRI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) (mdev_state->s[index].rxtx.head ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mdev_state->s[index].rxtx.tail)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #if defined(DEBUG_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pr_err("Serial port %d: IER_THRI write\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mtty_trigger_interrupt(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mutex_unlock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case UART_FCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mdev_state->s[index].fcr = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mutex_lock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (data & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* clear loop back FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mdev_state->s[index].rxtx.count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mdev_state->s[index].rxtx.head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mdev_state->s[index].rxtx.tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mutex_unlock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) switch (data & UART_FCR_TRIGGER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case UART_FCR_TRIGGER_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mdev_state->s[index].intr_trigger_level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case UART_FCR_TRIGGER_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mdev_state->s[index].intr_trigger_level = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case UART_FCR_TRIGGER_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mdev_state->s[index].intr_trigger_level = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case UART_FCR_TRIGGER_14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mdev_state->s[index].intr_trigger_level = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Set trigger level to 1 otherwise or implement timer with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * timeout of 4 characters and on expiring that timer set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Recevice data timeout in IIR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mdev_state->s[index].intr_trigger_level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (data & UART_FCR_ENABLE_FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mdev_state->s[index].max_fifo_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mdev_state->s[index].intr_trigger_level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case UART_LCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (data & UART_LCR_DLAB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mdev_state->s[index].dlab = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mdev_state->s[index].divisor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mdev_state->s[index].dlab = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mdev_state->s[index].uart_reg[offset] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case UART_MCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mdev_state->s[index].uart_reg[offset] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (data & UART_MCR_OUT2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #if defined(DEBUG_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pr_err("Serial port %d: MCR_OUT2 write\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mtty_trigger_interrupt(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) (data & (UART_MCR_RTS | UART_MCR_DTR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #if defined(DEBUG_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pr_err("Serial port %d: MCR RTS/DTR write\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mtty_trigger_interrupt(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case UART_LSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case UART_MSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case UART_SCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mdev_state->s[index].uart_reg[offset] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u16 offset, u8 *buf, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Handle read requests by guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case UART_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* if DLAB set, data is LSB of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (mdev_state->s[index].dlab) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *buf = (u8)mdev_state->s[index].divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mutex_lock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* return data in tx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (mdev_state->s[index].rxtx.head !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mdev_state->s[index].rxtx.tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *buf = mdev_state->s[index].rxtx.fifo[
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mdev_state->s[index].rxtx.tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mdev_state->s[index].rxtx.count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (mdev_state->s[index].rxtx.head ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mdev_state->s[index].rxtx.tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * Trigger interrupt if tx buffer empty interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * enabled and fifo is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #if defined(DEBUG_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pr_err("Serial port %d: Buffer Empty\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (mdev_state->s[index].uart_reg[UART_IER] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) UART_IER_THRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mtty_trigger_interrupt(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mutex_unlock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case UART_IER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (mdev_state->s[index].dlab) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *buf = (u8)(mdev_state->s[index].divisor >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *buf = mdev_state->s[index].uart_reg[offset] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case UART_IIR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 ier = mdev_state->s[index].uart_reg[UART_IER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mutex_lock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Interrupt priority 1: Parity, overrun, framing or break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *buf |= UART_IIR_RLSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Interrupt priority 2: Fifo trigger level reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if ((ier & UART_IER_RDI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) (mdev_state->s[index].rxtx.count >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mdev_state->s[index].intr_trigger_level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *buf |= UART_IIR_RDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Interrupt priotiry 3: transmitter holding register empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if ((ier & UART_IER_THRI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (mdev_state->s[index].rxtx.head ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mdev_state->s[index].rxtx.tail))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) *buf |= UART_IIR_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Interrupt priotiry 4: Modem status: CTS, DSR, RI or DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if ((ier & UART_IER_MSI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) (mdev_state->s[index].uart_reg[UART_MCR] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) (UART_MCR_RTS | UART_MCR_DTR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *buf |= UART_IIR_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* bit0: 0=> interrupt pending, 1=> no interrupt is pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (*buf == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) *buf = UART_IIR_NO_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* set bit 6 & 7 to be 16550 compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *buf |= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mutex_unlock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case UART_LCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case UART_MCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *buf = mdev_state->s[index].uart_reg[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case UART_LSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u8 lsr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mutex_lock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* atleast one char in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (mdev_state->s[index].rxtx.head !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mdev_state->s[index].rxtx.tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) lsr |= UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* if FIFO overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (mdev_state->s[index].overrun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) lsr |= UART_LSR_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* transmit FIFO empty and tramsitter empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (mdev_state->s[index].rxtx.head ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mdev_state->s[index].rxtx.tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) lsr |= UART_LSR_TEMT | UART_LSR_THRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mutex_unlock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *buf = lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case UART_MSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *buf = UART_MSR_DSR | UART_MSR_DDSR | UART_MSR_DCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) mutex_lock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* if AFE is 1 and FIFO have space, set CTS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (mdev_state->s[index].uart_reg[UART_MCR] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) UART_MCR_AFE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (mdev_state->s[index].rxtx.count <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mdev_state->s[index].max_fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *buf |= UART_MSR_CTS | UART_MSR_DCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *buf |= UART_MSR_CTS | UART_MSR_DCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mutex_unlock(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case UART_SCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *buf = mdev_state->s[index].uart_reg[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static void mdev_read_base(struct mdev_state *mdev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int index, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 start_lo, start_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 mem_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pos = PCI_BASE_ADDRESS_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) for (index = 0; index <= VFIO_PCI_BAR5_REGION_INDEX; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!mdev_state->region_info[index].size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) start_lo = (*(u32 *)(mdev_state->vconfig + pos)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mem_type = (*(u32 *)(mdev_state->vconfig + pos)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PCI_BASE_ADDRESS_MEM_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) switch (mem_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case PCI_BASE_ADDRESS_MEM_TYPE_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) start_hi = (*(u32 *)(mdev_state->vconfig + pos + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) pos += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case PCI_BASE_ADDRESS_MEM_TYPE_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case PCI_BASE_ADDRESS_MEM_TYPE_1M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* 1M mem BAR treated as 32-bit BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* mem unknown type treated as 32-bit BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) start_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pos += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mdev_state->region_info[index].start = ((u64)start_hi << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) start_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static ssize_t mdev_access(struct mdev_device *mdev, u8 *buf, size_t count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) loff_t pos, bool is_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct mdev_state *mdev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) loff_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!mdev || !buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mdev_state = mdev_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!mdev_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pr_err("%s mdev_state not found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mutex_lock(&mdev_state->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) index = MTTY_VFIO_PCI_OFFSET_TO_INDEX(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) offset = pos & MTTY_VFIO_PCI_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case VFIO_PCI_CONFIG_REGION_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #if defined(DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pr_info("%s: PCI config space %s at offset 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) __func__, is_write ? "write" : "read", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (is_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dump_buffer(buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) handle_pci_cfg_write(mdev_state, offset, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) memcpy(buf, (mdev_state->vconfig + offset), count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dump_buffer(buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case VFIO_PCI_BAR0_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (!mdev_state->region_info[index].start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mdev_read_base(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (is_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dump_buffer(buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #if defined(DEBUG_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pr_info("%s: BAR%d WR @0x%llx %s val:0x%02x dlab:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __func__, index, offset, wr_reg[offset],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *buf, mdev_state->s[index].dlab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) handle_bar_write(index, mdev_state, offset, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) handle_bar_read(index, mdev_state, offset, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dump_buffer(buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #if defined(DEBUG_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pr_info("%s: BAR%d RD @0x%llx %s val:0x%02x dlab:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __func__, index, offset, rd_reg[offset],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *buf, mdev_state->s[index].dlab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) goto accessfailed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) accessfailed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mutex_unlock(&mdev_state->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int mtty_create(struct kobject *kobj, struct mdev_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct mdev_state *mdev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) char name[MTTY_STRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int nr_ports = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) snprintf(name, MTTY_STRING_LEN, "%s-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_driver_string(mdev_parent_dev(mdev)), i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!strcmp(kobj->name, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) nr_ports = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!nr_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (mdev_state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mdev_state->nr_ports = nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mdev_state->irq_index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mutex_init(&mdev_state->rxtx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (mdev_state->vconfig == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) kfree(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mutex_init(&mdev_state->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mdev_state->mdev = mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mdev_set_drvdata(mdev, mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mtty_create_config_space(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mutex_lock(&mdev_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) list_add(&mdev_state->next, &mdev_devices_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mutex_unlock(&mdev_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int mtty_remove(struct mdev_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct mdev_state *mds, *tmp_mds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mutex_lock(&mdev_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) list_for_each_entry_safe(mds, tmp_mds, &mdev_devices_list, next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (mdev_state == mds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) list_del(&mdev_state->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mdev_set_drvdata(mdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) kfree(mdev_state->vconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) kfree(mdev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mutex_unlock(&mdev_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int mtty_reset(struct mdev_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct mdev_state *mdev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mdev_state = mdev_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!mdev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pr_info("%s: called\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static ssize_t mtty_read(struct mdev_device *mdev, char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) unsigned int done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) size_t filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (count >= 4 && !(*ppos % 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) *ppos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (copy_to_user(buf, &val, sizeof(val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) goto read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) filled = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) } else if (count >= 2 && !(*ppos % 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) *ppos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (copy_to_user(buf, &val, sizeof(val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) filled = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *ppos, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) goto read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (copy_to_user(buf, &val, sizeof(val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) filled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) count -= filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) done += filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) *ppos += filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) buf += filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) read_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static ssize_t mtty_write(struct mdev_device *mdev, const char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unsigned int done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) size_t filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (count >= 4 && !(*ppos % 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (copy_from_user(&val, buf, sizeof(val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) goto write_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) *ppos, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) goto write_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) filled = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else if (count >= 2 && !(*ppos % 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (copy_from_user(&val, buf, sizeof(val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) goto write_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *ppos, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto write_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) filled = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (copy_from_user(&val, buf, sizeof(val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) goto write_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) *ppos, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) goto write_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) filled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) count -= filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) done += filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *ppos += filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) buf += filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) write_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int mtty_set_irqs(struct mdev_device *mdev, uint32_t flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) unsigned int index, unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned int count, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct mdev_state *mdev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mdev_state = mdev_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!mdev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mutex_lock(&mdev_state->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case VFIO_PCI_INTX_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case VFIO_IRQ_SET_ACTION_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case VFIO_IRQ_SET_ACTION_UNMASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case VFIO_IRQ_SET_ACTION_TRIGGER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (flags & VFIO_IRQ_SET_DATA_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) pr_info("%s: disable INTx\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (mdev_state->intx_evtfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) eventfd_ctx_put(mdev_state->intx_evtfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int fd = *(int *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (fd > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct eventfd_ctx *evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) evt = eventfd_ctx_fdget(fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (IS_ERR(evt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = PTR_ERR(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) mdev_state->intx_evtfd = evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mdev_state->irq_fd = fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mdev_state->irq_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case VFIO_PCI_MSI_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) case VFIO_IRQ_SET_ACTION_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) case VFIO_IRQ_SET_ACTION_UNMASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) case VFIO_IRQ_SET_ACTION_TRIGGER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (flags & VFIO_IRQ_SET_DATA_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (mdev_state->msi_evtfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) eventfd_ctx_put(mdev_state->msi_evtfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pr_info("%s: disable MSI\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) mdev_state->irq_index = VFIO_PCI_INTX_IRQ_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int fd = *(int *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct eventfd_ctx *evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (fd <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (mdev_state->msi_evtfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) evt = eventfd_ctx_fdget(fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (IS_ERR(evt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = PTR_ERR(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mdev_state->msi_evtfd = evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) mdev_state->irq_fd = fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) mdev_state->irq_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case VFIO_PCI_MSIX_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pr_info("%s: MSIX_IRQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) case VFIO_PCI_ERR_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) pr_info("%s: ERR_IRQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) case VFIO_PCI_REQ_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pr_info("%s: REQ_IRQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) mutex_unlock(&mdev_state->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static int mtty_trigger_interrupt(struct mdev_state *mdev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if ((mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) (!mdev_state->msi_evtfd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) else if ((mdev_state->irq_index == VFIO_PCI_INTX_IRQ_INDEX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) (!mdev_state->intx_evtfd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) pr_info("%s: Intr eventfd not found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = eventfd_signal(mdev_state->msi_evtfd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = eventfd_signal(mdev_state->intx_evtfd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #if defined(DEBUG_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pr_info("Intx triggered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) pr_err("%s: eventfd signal failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int mtty_get_region_info(struct mdev_device *mdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct vfio_region_info *region_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u16 *cap_type_id, void **cap_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) unsigned int size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct mdev_state *mdev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u32 bar_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mdev_state = mdev_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!mdev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) bar_index = region_info->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (bar_index >= VFIO_PCI_NUM_REGIONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mutex_lock(&mdev_state->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) switch (bar_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) case VFIO_PCI_CONFIG_REGION_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) size = MTTY_CONFIG_SPACE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case VFIO_PCI_BAR0_REGION_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) size = MTTY_IO_BAR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case VFIO_PCI_BAR1_REGION_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (mdev_state->nr_ports == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) size = MTTY_IO_BAR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) mdev_state->region_info[bar_index].size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mdev_state->region_info[bar_index].vfio_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) region_info->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) region_info->offset = MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) region_info->flags = VFIO_REGION_INFO_FLAG_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) VFIO_REGION_INFO_FLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mutex_unlock(&mdev_state->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static int mtty_get_irq_info(struct mdev_device *mdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct vfio_irq_info *irq_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) switch (irq_info->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) case VFIO_PCI_INTX_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) case VFIO_PCI_MSI_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case VFIO_PCI_REQ_IRQ_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) irq_info->flags = VFIO_IRQ_INFO_EVENTFD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) irq_info->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (irq_info->index == VFIO_PCI_INTX_IRQ_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) irq_info->flags |= (VFIO_IRQ_INFO_MASKABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) VFIO_IRQ_INFO_AUTOMASKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) irq_info->flags |= VFIO_IRQ_INFO_NORESIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int mtty_get_device_info(struct mdev_device *mdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct vfio_device_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static long mtty_ioctl(struct mdev_device *mdev, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned long minsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct mdev_state *mdev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) mdev_state = mdev_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!mdev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) case VFIO_DEVICE_GET_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct vfio_device_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) minsz = offsetofend(struct vfio_device_info, num_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (copy_from_user(&info, (void __user *)arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (info.argsz < minsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = mtty_get_device_info(mdev, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) memcpy(&mdev_state->dev_info, &info, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (copy_to_user((void __user *)arg, &info, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) case VFIO_DEVICE_GET_REGION_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct vfio_region_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) u16 cap_type_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) void *cap_type = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) minsz = offsetofend(struct vfio_region_info, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (copy_from_user(&info, (void __user *)arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (info.argsz < minsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ret = mtty_get_region_info(mdev, &info, &cap_type_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) &cap_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (copy_to_user((void __user *)arg, &info, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case VFIO_DEVICE_GET_IRQ_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct vfio_irq_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) minsz = offsetofend(struct vfio_irq_info, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (copy_from_user(&info, (void __user *)arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if ((info.argsz < minsz) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) (info.index >= mdev_state->dev_info.num_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = mtty_get_irq_info(mdev, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (copy_to_user((void __user *)arg, &info, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case VFIO_DEVICE_SET_IRQS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct vfio_irq_set hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u8 *data = NULL, *ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) size_t data_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) minsz = offsetofend(struct vfio_irq_set, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (copy_from_user(&hdr, (void __user *)arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = vfio_set_irqs_validate_and_prepare(&hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) mdev_state->dev_info.num_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) VFIO_PCI_NUM_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) &data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ptr = data = memdup_user((void __user *)(arg + minsz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ret = mtty_set_irqs(mdev, hdr.flags, hdr.index, hdr.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) hdr.count, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) kfree(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) case VFIO_DEVICE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return mtty_reset(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static int mtty_open(struct mdev_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) pr_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static void mtty_close(struct mdev_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) pr_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) sample_mtty_dev_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return sprintf(buf, "This is phy device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static DEVICE_ATTR_RO(sample_mtty_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static struct attribute *mtty_dev_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) &dev_attr_sample_mtty_dev.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static const struct attribute_group mtty_dev_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .name = "mtty_dev",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .attrs = mtty_dev_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static const struct attribute_group *mtty_dev_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) &mtty_dev_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) sample_mdev_dev_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (mdev_from_dev(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return sprintf(buf, "This is MDEV %s\n", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return sprintf(buf, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static DEVICE_ATTR_RO(sample_mdev_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static struct attribute *mdev_dev_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) &dev_attr_sample_mdev_dev.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static const struct attribute_group mdev_dev_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .name = "vendor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .attrs = mdev_dev_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static const struct attribute_group *mdev_dev_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) &mdev_dev_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) name_show(struct kobject *kobj, struct device *dev, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) char name[MTTY_STRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) const char *name_str[2] = {"Single port serial", "Dual port serial"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) snprintf(name, MTTY_STRING_LEN, "%s-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev_driver_string(dev), i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!strcmp(kobj->name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return sprintf(buf, "%s\n", name_str[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static MDEV_TYPE_ATTR_RO(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) available_instances_show(struct kobject *kobj, struct device *dev, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) char name[MTTY_STRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct mdev_state *mds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) int ports = 0, used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) snprintf(name, MTTY_STRING_LEN, "%s-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_driver_string(dev), i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (!strcmp(kobj->name, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ports = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (!ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) list_for_each_entry(mds, &mdev_devices_list, next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) used += mds->nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return sprintf(buf, "%d\n", (MAX_MTTYS - used)/ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static MDEV_TYPE_ATTR_RO(available_instances);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static ssize_t device_api_show(struct kobject *kobj, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static MDEV_TYPE_ATTR_RO(device_api);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static struct attribute *mdev_types_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) &mdev_type_attr_name.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) &mdev_type_attr_device_api.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) &mdev_type_attr_available_instances.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static struct attribute_group mdev_type_group1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .name = "1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .attrs = mdev_types_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static struct attribute_group mdev_type_group2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .name = "2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .attrs = mdev_types_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static struct attribute_group *mdev_type_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) &mdev_type_group1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) &mdev_type_group2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static const struct mdev_parent_ops mdev_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .dev_attr_groups = mtty_dev_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .mdev_attr_groups = mdev_dev_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .supported_type_groups = mdev_type_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .create = mtty_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .remove = mtty_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .open = mtty_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .release = mtty_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .read = mtty_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .write = mtty_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .ioctl = mtty_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static void mtty_device_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_dbg(dev, "mtty: released\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static int __init mtty_dev_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pr_info("mtty_dev: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) memset(&mtty_dev, 0, sizeof(mtty_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) idr_init(&mtty_dev.vd_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ret = alloc_chrdev_region(&mtty_dev.vd_devt, 0, MINORMASK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) MTTY_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) pr_err("Error: failed to register mtty_dev, err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) cdev_init(&mtty_dev.vd_cdev, &vd_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) cdev_add(&mtty_dev.vd_cdev, mtty_dev.vd_devt, MINORMASK + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) pr_info("major_number:%d\n", MAJOR(mtty_dev.vd_devt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) mtty_dev.vd_class = class_create(THIS_MODULE, MTTY_CLASS_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (IS_ERR(mtty_dev.vd_class)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pr_err("Error: failed to register mtty_dev class\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ret = PTR_ERR(mtty_dev.vd_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) goto failed1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) mtty_dev.dev.class = mtty_dev.vd_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) mtty_dev.dev.release = mtty_device_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev_set_name(&mtty_dev.dev, "%s", MTTY_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = device_register(&mtty_dev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) goto failed2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ret = mdev_register_device(&mtty_dev.dev, &mdev_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) goto failed3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) mutex_init(&mdev_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) INIT_LIST_HEAD(&mdev_devices_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) goto all_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) failed3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) device_unregister(&mtty_dev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) failed2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) class_destroy(mtty_dev.vd_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) failed1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) cdev_del(&mtty_dev.vd_cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) all_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static void __exit mtty_dev_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) mtty_dev.dev.bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) mdev_unregister_device(&mtty_dev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) device_unregister(&mtty_dev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) idr_destroy(&mtty_dev.vd_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) cdev_del(&mtty_dev.vd_cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) class_destroy(mtty_dev.vd_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) mtty_dev.vd_class = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) pr_info("mtty_dev: Unloaded!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) module_init(mtty_dev_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) module_exit(mtty_dev_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) MODULE_INFO(supported, "Test driver that simulate serial port over PCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) MODULE_VERSION(VERSION_STRING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) MODULE_AUTHOR(DRIVER_AUTHOR);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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