^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* eBPF instruction mini library */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef __BPF_INSN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define __BPF_INSN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) struct bpf_insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BPF_ALU64_REG(OP, DST, SRC) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .code = BPF_ALU64 | BPF_OP(OP) | BPF_X, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BPF_ALU32_REG(OP, DST, SRC) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .code = BPF_ALU | BPF_OP(OP) | BPF_X, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* ALU ops on immediates, bpf_add|sub|...: dst_reg += imm32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BPF_ALU64_IMM(OP, DST, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .code = BPF_ALU64 | BPF_OP(OP) | BPF_K, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BPF_ALU32_IMM(OP, DST, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .code = BPF_ALU | BPF_OP(OP) | BPF_K, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Short form of mov, dst_reg = src_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BPF_MOV64_REG(DST, SRC) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .code = BPF_ALU64 | BPF_MOV | BPF_X, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BPF_MOV32_REG(DST, SRC) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .code = BPF_ALU | BPF_MOV | BPF_X, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Short form of mov, dst_reg = imm32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BPF_MOV64_IMM(DST, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .code = BPF_ALU64 | BPF_MOV | BPF_K, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BPF_MOV32_IMM(DST, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .code = BPF_ALU | BPF_MOV | BPF_K, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* BPF_LD_IMM64 macro encodes single 'load 64-bit immediate' insn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BPF_LD_IMM64(DST, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BPF_LD_IMM64_RAW(DST, 0, IMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BPF_LD_IMM64_RAW(DST, SRC, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .code = BPF_LD | BPF_DW | BPF_IMM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .imm = (__u32) (IMM) }), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .code = 0, /* zero is reserved opcode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .dst_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .imm = ((__u64) (IMM)) >> 32 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifndef BPF_PSEUDO_MAP_FD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define BPF_PSEUDO_MAP_FD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* pseudo BPF_LD_IMM64 insn used to refer to process-local map_fd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BPF_LD_MAP_FD(DST, MAP_FD) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) BPF_LD_IMM64_RAW(DST, BPF_PSEUDO_MAP_FD, MAP_FD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Direct packet access, R0 = *(uint *) (skb->data + imm32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BPF_LD_ABS(SIZE, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .code = BPF_LD | BPF_SIZE(SIZE) | BPF_ABS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .dst_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Memory load, dst_reg = *(uint *) (src_reg + off16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BPF_LDX_MEM(SIZE, DST, SRC, OFF) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .code = BPF_LDX | BPF_SIZE(SIZE) | BPF_MEM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Memory store, *(uint *) (dst_reg + off16) = src_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BPF_STX_MEM(SIZE, DST, SRC, OFF) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .code = BPF_STX | BPF_SIZE(SIZE) | BPF_MEM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Atomic memory add, *(uint *)(dst_reg + off16) += src_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BPF_STX_XADD(SIZE, DST, SRC, OFF) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .code = BPF_STX | BPF_SIZE(SIZE) | BPF_XADD, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Memory store, *(uint *) (dst_reg + off16) = imm32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BPF_ST_MEM(SIZE, DST, OFF, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .code = BPF_ST | BPF_SIZE(SIZE) | BPF_MEM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Conditional jumps against registers, if (dst_reg 'op' src_reg) goto pc + off16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BPF_JMP_REG(OP, DST, SRC, OFF) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .code = BPF_JMP | BPF_OP(OP) | BPF_X, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Like BPF_JMP_REG, but with 32-bit wide operands for comparison. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BPF_JMP32_REG(OP, DST, SRC, OFF) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .code = BPF_JMP32 | BPF_OP(OP) | BPF_X, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Conditional jumps against immediates, if (dst_reg 'op' imm32) goto pc + off16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BPF_JMP_IMM(OP, DST, IMM, OFF) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .code = BPF_JMP | BPF_OP(OP) | BPF_K, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Like BPF_JMP_IMM, but with 32-bit wide operands for comparison. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BPF_JMP32_IMM(OP, DST, IMM, OFF) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .code = BPF_JMP32 | BPF_OP(OP) | BPF_K, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Raw code statement block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BPF_RAW_INSN(CODE, DST, SRC, OFF, IMM) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .code = CODE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .dst_reg = DST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .src_reg = SRC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .off = OFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .imm = IMM })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Program exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BPF_EXIT_INSN() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ((struct bpf_insn) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .code = BPF_JMP | BPF_EXIT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .dst_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .src_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .imm = 0 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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