Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 1999 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2000 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/stmp_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STMP_MODULE_CLKGATE	(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STMP_MODULE_SFTRST	(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * Clear the bit and poll it cleared.  This is usually called with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * (bit 30).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	int timeout = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	writel(mask, addr + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	while ((readl(addr) & mask) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		/* nothing */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	return !timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int stmp_reset_block(void __iomem *reset_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	int timeout = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	/* clear and poll SFTRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	/* clear CLKGATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	/* set SFTRST to reset the block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* poll CLKGATE becoming set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		/* nothing */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	if (unlikely(!timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	/* clear and poll SFTRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	/* clear and poll CLKGATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) EXPORT_SYMBOL(stmp_reset_block);