^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Note: I added some stuff for use with gnupg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1991, 1992, 1993, 1994, 1996, 1998,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * it under the terms of the GNU Library General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * You should have received a copy of the GNU Library General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * along with this file; see the file COPYING.LIB. If not, write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * MA 02111-1307, USA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/count_zeros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* You have to define the following before including this file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * UWtype -- An unsigned type, default type for operations (typically a "word")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * UHWtype -- An unsigned type, at least half the size of UWtype.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * UDWtype -- An unsigned type, at least twice as large a UWtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * W_TYPE_SIZE -- size in bits of UWtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * SItype, USItype -- Signed and unsigned 32 bit types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DItype, UDItype -- Signed and unsigned 64 bit types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * On a 32 bit machine UWtype should typically be USItype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * on a 64 bit machine, UWtype should typically be UDItype.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define __BITS4 (W_TYPE_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* This is used to make sure no undesirable sharing between different libraries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) that use this file takes place. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef __MPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define __MPN(x) __##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Define auxiliary asm macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * word product in HIGH_PROD and LOW_PROD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * UDWtype product. This is just a variant of umul_ppmm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * denominator) divides a UDWtype, composed by the UWtype integers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * than DENOMINATOR for correct operation. If, in addition, the most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * significant bit of DENOMINATOR must be 1, then the pre-processor symbol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * UDIV_NEEDS_NORMALIZATION is defined to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * denominator). Like udiv_qrnnd but the numbers are signed. The quotient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * is rounded towards 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 5) count_leading_zeros(count, x) counts the number of zero-bits from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * msb to the first non-zero bit in the UWtype X. This is the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * steps X needs to be shifted left to set the msb. Undefined for X == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * from the least significant end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * high_addend_2, low_addend_2) adds two UWtype integers, composed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * (i.e. carry out) is not stored anywhere, and is lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * and is lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * If any of these macros are left undefined for a particular CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * C macros are used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* The CPUs come in alphabetical order below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Please add support for more CPUs here, or improve the current support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * for the CPUs below! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #if defined(__GNUC__) && !defined(NO_ASM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* We sometimes need to clobber "cc" with gcc2, but that would not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) understood by gcc1. Use cpp to avoid major code duplication. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #if __GNUC__ < 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define __CLOBBER_CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define __AND_CLOBBER_CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #else /* __GNUC__ >= 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define __CLOBBER_CC : "cc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define __AND_CLOBBER_CC , "cc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* __GNUC__ < 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ************** A29K *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #if (defined(__a29k__) || defined(_AM29K)) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __asm__ ("add %1,%4,%5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "addc %0,%2,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) : "%r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "rI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "%r" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "rI" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __asm__ ("sub %1,%4,%5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "subc %0,%2,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) : "r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "rI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "r" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "rI" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define umul_ppmm(xh, xl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) USItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __asm__ ("multiplu %0,%1,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) : "=r" ((USItype)(xl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) : "r" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "r" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __asm__ ("multmu %0,%1,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) : "=r" ((USItype)(xh)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) : "r" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "r" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __asm__ ("dividu %0,%3,%4" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) : "=r" ((USItype)(q)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "=q" ((USItype)(r)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) : "1" ((USItype)(n1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "r" ((USItype)(n0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "r" ((USItype)(d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif /* __a29k__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #if defined(__alpha) && W_TYPE_SIZE == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define umul_ppmm(ph, pl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) UDItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (ph) = __builtin_alpha_umulh(__m0, __m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (pl) = __m0 * __m1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define UMUL_TIME 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifndef LONGLONG_STANDALONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) do { UDItype __r; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (q) = __udiv_qrnnd(&__r, (n1), (n0), (d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (r) = __r; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) extern UDItype __udiv_qrnnd(UDItype *, UDItype, UDItype, UDItype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define UDIV_TIME 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif /* LONGLONG_STANDALONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif /* __alpha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ************** ARM ******************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #if defined(__arm__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __asm__ ("adds %1, %4, %5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "adc %0, %2, %3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) : "%r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "rI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "%r" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "rI" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __asm__ ("subs %1, %4, %5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "sbc %0, %2, %3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) : "r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "rI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "r" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "rI" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #if defined __ARM_ARCH_2__ || defined __ARM_ARCH_3__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define umul_ppmm(xh, xl, a, b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __asm__ ("@ Inlined umul_ppmm\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "mov %|r0, %2, lsr #16 @ AAAA\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "mov %|r2, %3, lsr #16 @ BBBB\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "bic %|r1, %2, %|r0, lsl #16 @ aaaa\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "bic %0, %3, %|r2, lsl #16 @ bbbb\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "mul %1, %|r1, %|r2 @ aaaa * BBBB\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "mul %|r2, %|r0, %|r2 @ AAAA * BBBB\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "mul %|r1, %0, %|r1 @ aaaa * bbbb\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "mul %0, %|r0, %0 @ AAAA * bbbb\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "adds %|r0, %1, %0 @ central sum\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "addcs %|r2, %|r2, #65536\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "adds %1, %|r1, %|r0, lsl #16\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "adc %0, %|r2, %|r0, lsr #16" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) : "=&r" (xh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "=r" (xl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) : "r" ((USItype)(a)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "r" ((USItype)(b)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) : "r0", "r1", "r2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define umul_ppmm(xh, xl, a, b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __asm__ ("@ Inlined umul_ppmm\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "umull %1, %0, %2, %3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) : "=&r" (xh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "=&r" (xl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) : "r" ((USItype)(a)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "r" ((USItype)(b)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) : "r0", "r1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define UMUL_TIME 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define UDIV_TIME 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif /* __arm__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ************** CLIPPER **************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #if defined(__clipper__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ({union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct {USItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __asm__ ("mulwux %2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) : "=r" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) : "%0" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "r" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define smul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ({union {DItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct {SItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __asm__ ("mulwx %2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) : "=r" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) : "%0" ((SItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "r" ((SItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define __umulsidi3(u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ({UDItype __w; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __asm__ ("mulwux %2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) : "=r" (__w) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) : "%0" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "r" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __w; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif /* __clipper__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ************** GMICRO ***************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #if defined(__gmicro__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __asm__ ("add.w %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "addx %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) : "=g" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "=&g" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) : "%0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "%1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __asm__ ("sub.w %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "subx %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) : "=g" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "=&g" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) : "0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define umul_ppmm(ph, pl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __asm__ ("mulx %3,%0,%1" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) : "=g" ((USItype)(ph)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "=r" ((USItype)(pl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) : "%0" ((USItype)(m0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "g" ((USItype)(m1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define udiv_qrnnd(q, r, nh, nl, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __asm__ ("divx %4,%0,%1" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) : "=g" ((USItype)(q)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "=r" ((USItype)(r)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) : "1" ((USItype)(nh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "0" ((USItype)(nl)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "g" ((USItype)(d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ************** HPPA *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #if defined(__hppa) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) __asm__ ("add %4,%5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "addc %2,%3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) : "%rM" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "rM" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "%rM" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "rM" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __asm__ ("sub %4,%5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "subb %2,%3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) : "rM" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "rM" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "rM" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "rM" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #if 0 && defined(_PA_RISC1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* xmpyu uses floating point register which is not allowed in Linux kernel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define umul_ppmm(wh, wl, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct {USItype __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __asm__ ("xmpyu %1,%2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) : "=*f" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) : "*f" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "*f" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (wh) = __xx.__i.__h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (wl) = __xx.__i.__l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define UMUL_TIME 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define UDIV_TIME 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define UMUL_TIME 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define UDIV_TIME 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #if 0 /* #ifndef LONGLONG_STANDALONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) do { USItype __r; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (q) = __udiv_qrnnd(&__r, (n1), (n0), (d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) (r) = __r; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) extern USItype __udiv_qrnnd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif /* LONGLONG_STANDALONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif /* hppa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ************** I370 *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #if (defined(__i370__) || defined(__mvs__)) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define umul_ppmm(xh, xl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct {USItype __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) USItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) __asm__ ("mr %0,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) : "=r" (__xx.__i.__h), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "=r" (__xx.__i.__l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) : "%1" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "r" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (xh) += ((((SItype) __m0 >> 31) & __m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) + (((SItype) __m1 >> 31) & __m0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define smul_ppmm(xh, xl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) union {DItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct {USItype __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __asm__ ("mr %0,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) : "=r" (__xx.__i.__h), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "=r" (__xx.__i.__l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) : "%1" (m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "r" (m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define sdiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) union {DItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct {USItype __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __xx.__i.__h = n1; __xx.__i.__l = n0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) __asm__ ("dr %0,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) : "=r" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) : "0" (__xx.__ll), "r" (d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ************** I386 *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #undef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #if (defined(__i386__) || defined(__i486__)) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __asm__ ("addl %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "adcl %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) : "%0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "%1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) __asm__ ("subl %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "sbbl %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) : "0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __asm__ ("mull %3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) : "=a" (w0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "=d" (w1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) : "%0" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "rm" ((USItype)(v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __asm__ ("divl %4" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) : "=a" (q), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "=d" (r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) : "0" ((USItype)(n0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "1" ((USItype)(n1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "rm" ((USItype)(d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #ifndef UMUL_TIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define UMUL_TIME 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #ifndef UDIV_TIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define UDIV_TIME 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #endif /* 80x86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ************** I860 *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #if defined(__i860__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define rshift_rhlc(r, h, l, c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) __asm__ ("shr %3,r0,r0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "shrd %1,%2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "=r" (r) : "r" (h), "r" (l), "rn" (c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #endif /* i860 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ************** I960 *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #if defined(__i960__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) __asm__ ("cmpo 1,0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "addc %5,%4,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "addc %3,%2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) : "%dI" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "dI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "%dI" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "dI" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __asm__ ("cmpo 0,0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "subc %5,%4,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "subc %3,%2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) : "dI" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "dI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "dI" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "dI" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ({union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct {USItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) __asm__ ("emul %2,%1,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) : "=d" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) : "%dI" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "dI" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define __umulsidi3(u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ({UDItype __w; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __asm__ ("emul %2,%1,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) : "=d" (__w) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) : "%dI" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "dI" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __w; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define udiv_qrnnd(q, r, nh, nl, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct {USItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } __nn; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __nn.__i.__h = (nh); __nn.__i.__l = (nl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __asm__ ("ediv %d,%n,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) : "=d" (__rq.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) : "dI" (__nn.__ll), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "dI" ((USItype)(d))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (r) = __rq.__i.__l; (q) = __rq.__i.__h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #if defined(__i960mx) /* what is the proper symbol to test??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define rshift_rhlc(r, h, l, c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct {USItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } __nn; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __nn.__i.__h = (h); __nn.__i.__l = (l); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) __asm__ ("shre %2,%1,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #endif /* i960mx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif /* i960 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ************** 68000 ****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #if (defined(__mc68000__) || defined(__mc68020__) || defined(__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __asm__ ("add%.l %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "addx%.l %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) : "=d" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "=&d" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) : "%0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "d" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "%1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __asm__ ("sub%.l %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "subx%.l %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) : "=d" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "=&d" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) : "0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "d" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #if (defined(__mc68020__) || defined(__NeXT__) || defined(mc68020))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) __asm__ ("mulu%.l %3,%1:%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) : "=d" ((USItype)(w0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "=d" ((USItype)(w1)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) : "%0" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "dmi" ((USItype)(v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define UMUL_TIME 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __asm__ ("divu%.l %4,%1:%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) : "=d" ((USItype)(q)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "=d" ((USItype)(r)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) : "0" ((USItype)(n0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "1" ((USItype)(n1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "dmi" ((USItype)(d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define UDIV_TIME 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define sdiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) __asm__ ("divs%.l %4,%1:%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) : "=d" ((USItype)(q)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "=d" ((USItype)(r)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) : "0" ((USItype)(n0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "1" ((USItype)(n1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "dmi" ((USItype)(d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #else /* not mc68020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define umul_ppmm(xh, xl, a, b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) do { USItype __umul_tmp1, __umul_tmp2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __asm__ ("| Inlined umul_ppmm\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "move%.l %5,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "move%.l %2,%0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "move%.w %3,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "swap %3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "swap %0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "mulu %2,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "mulu %3,%0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "mulu %2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) "swap %2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "mulu %5,%2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "add%.l %3,%2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "jcc 1f\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "add%.l %#0x10000,%0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "1: move%.l %2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "clr%.w %2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "swap %2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "swap %3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "clr%.w %3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "add%.l %3,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "addx%.l %2,%0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "| End inlined umul_ppmm" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) : "%2" ((USItype)(a)), "d" ((USItype)(b))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define UMUL_TIME 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define UDIV_TIME 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #endif /* not mc68020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif /* mc68000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ************** 88000 ****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #if defined(__m88000__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) __asm__ ("addu.co %1,%r4,%r5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "addu.ci %0,%r2,%r3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) : "%rJ" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) "rJ" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "%rJ" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) "rJ" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) __asm__ ("subu.co %1,%r4,%r5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "subu.ci %0,%r2,%r3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) : "rJ" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "rJ" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "rJ" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "rJ" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #if defined(__m88110__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define umul_ppmm(wh, wl, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct {USItype __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __asm__ ("mulu.d %0,%1,%2" : "=r" (__x.__ll) : "r" (u), "r" (v)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) (wh) = __x.__i.__h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) (wl) = __x.__i.__l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ({union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct {USItype __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) } __x, __q; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __x.__i.__h = (n1); __x.__i.__l = (n0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __asm__ ("divu.d %0,%1,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) : "=r" (__q.__ll) : "r" (__x.__ll), "r" (d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) (r) = (n0) - __q.__l * (d); (q) = __q.__l; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define UMUL_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define UDIV_TIME 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define UMUL_TIME 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define UDIV_TIME 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #endif /* __m88110__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #endif /* __m88000__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ************** MIPS *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #if defined(__mips__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) UDItype __ll = (UDItype)(u) * (v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) w1 = __ll >> 32; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) w0 = __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define UMUL_TIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define UDIV_TIME 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif /* __mips__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ************** MIPS/64 **************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #if (defined(__mips) && __mips >= 3) && W_TYPE_SIZE == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #if defined(__mips_isa_rev) && __mips_isa_rev >= 6 && defined(CONFIG_CC_IS_GCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * GCC ends up emitting a __multi3 intrinsic call for MIPS64r6 with the plain C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * code below, so we special case MIPS64r6 until the compiler can do better.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) __asm__ ("dmulu %0,%1,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) : "=d" ((UDItype)(w0)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) : "d" ((UDItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "d" ((UDItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __asm__ ("dmuhu %0,%1,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) : "=d" ((UDItype)(w1)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) : "d" ((UDItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "d" ((UDItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) typedef unsigned int __ll_UTItype __attribute__((mode(TI))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __ll_UTItype __ll = (__ll_UTItype)(u) * (v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) w1 = __ll >> 64; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) w0 = __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define UMUL_TIME 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define UDIV_TIME 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #endif /* __mips__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ************** 32000 ****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #if defined(__ns32000__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ({union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct {USItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) __asm__ ("meid %2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) : "=g" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) : "%0" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "g" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define __umulsidi3(u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ({UDItype __w; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) __asm__ ("meid %2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) : "=g" (__w) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) : "%0" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "g" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) __w; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ({union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct {USItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __asm__ ("deid %2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) : "=g" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) : "0" (__xx.__ll), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "g" ((USItype)(d))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #endif /* __ns32000__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ************** PPC ******************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #if (defined(_ARCH_PPC) || defined(_IBMR2)) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (__builtin_constant_p(bh) && (bh) == 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) : "%r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "%r" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) "rI" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) else if (__builtin_constant_p(bh) && (bh) == ~(USItype) 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) : "%r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "%r" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "rI" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) : "%r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "r" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "%r" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "rI" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (__builtin_constant_p(ah) && (ah) == 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) : "r" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "rI" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "r" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) else if (__builtin_constant_p(ah) && (ah) == ~(USItype) 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) : "r" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "rI" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "r" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) else if (__builtin_constant_p(bh) && (bh) == 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) : "r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "rI" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "r" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) else if (__builtin_constant_p(bh) && (bh) == ~(USItype) 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) : "r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "rI" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "r" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) : "r" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "r" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "rI" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "r" ((USItype)(bl))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #if defined(_ARCH_PPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define umul_ppmm(ph, pl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) USItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) __asm__ ("mulhwu %0,%1,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) : "=r" (ph) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) : "%r" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "r" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) (pl) = __m0 * __m1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define UMUL_TIME 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define smul_ppmm(ph, pl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) SItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) __asm__ ("mulhw %0,%1,%2" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) : "=r" ((SItype) ph) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) : "%r" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "r" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) (pl) = __m0 * __m1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define SMUL_TIME 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define UDIV_TIME 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define umul_ppmm(xh, xl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) USItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) __asm__ ("mul %0,%2,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) : "=r" ((USItype)(xh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "=q" ((USItype)(xl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) : "r" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "r" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) (xh) += ((((SItype) __m0 >> 31) & __m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) + (((SItype) __m1 >> 31) & __m0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define UMUL_TIME 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define smul_ppmm(xh, xl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) __asm__ ("mul %0,%2,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) : "=r" ((SItype)(xh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "=q" ((SItype)(xl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) : "r" (m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "r" (m1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define SMUL_TIME 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define sdiv_qrnnd(q, r, nh, nl, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) __asm__ ("div %0,%2,%4" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) : "=r" ((SItype)(q)), "=q" ((SItype)(r)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) : "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define UDIV_TIME 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #endif /* Power architecture variants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ************** PYR ******************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #if defined(__pyr__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) __asm__ ("addw %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "addwc %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) : "%0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "%1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) __asm__ ("subw %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "subwb %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) : "0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ({union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct {USItype __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) __asm__ ("movw %1,%R0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) "uemul %2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) : "=&r" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) : "g" ((USItype) (u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "g" ((USItype)(v))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #endif /* __pyr__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ************** RT/ROMP **************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #if defined(__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) __asm__ ("a %1,%5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "ae %0,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) : "%0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "r" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "%1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "r" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __asm__ ("s %1,%5\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "se %0,%3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) : "0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "r" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "r" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define umul_ppmm(ph, pl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) USItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) __asm__ ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "s r2,r2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "mts r10,%2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "m r2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "cas %0,r2,r0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "mfs r10,%1" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) : "=r" ((USItype)(ph)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "=r" ((USItype)(pl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) : "%r" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "r" (__m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) : "r2"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) (ph) += ((((SItype) __m0 >> 31) & __m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) + (((SItype) __m1 >> 31) & __m0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define UMUL_TIME 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define UDIV_TIME 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #endif /* RT/ROMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ************** SH2 ******************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #if (defined(__sh2__) || defined(__sh3__) || defined(__SH4__)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) __asm__ ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "dmulu.l %2,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "sts macl,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "sts mach,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) : "=r" ((USItype)(w1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) "=r" ((USItype)(w0)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) : "r" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) "r" ((USItype)(v)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) : "macl", "mach")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define UMUL_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ************** SPARC ****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #if defined(__sparc__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) __asm__ ("addcc %r4,%5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) "addx %r2,%3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) : "%rJ" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "rI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "%rJ" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "rI" ((USItype)(bl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) __CLOBBER_CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) __asm__ ("subcc %r4,%5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "subx %r2,%3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) : "=r" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) "=&r" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) : "rJ" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "rI" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) "rJ" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "rI" ((USItype)(bl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) __CLOBBER_CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #if defined(__sparc_v8__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Don't match immediate range because, 1) it is not often useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) 2) the 'I' flag thinks of the range as a 13 bit signed interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) while we want to match a 13 bit interval, sign extended to 32 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) but INTERPRETED AS UNSIGNED. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) __asm__ ("umul %2,%3,%1;rd %%y,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) : "=r" ((USItype)(w1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "=r" ((USItype)(w0)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) : "r" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) "r" ((USItype)(v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define UMUL_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #ifndef SUPERSPARC /* SuperSPARC's udiv only handles 53 bit dividends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) USItype __q; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) __asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) : "=r" ((USItype)(__q)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) : "r" ((USItype)(n1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) "r" ((USItype)(n0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "r" ((USItype)(d))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) (r) = (n0) - __q * (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) (q) = __q; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define UDIV_TIME 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #endif /* SUPERSPARC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #else /* ! __sparc_v8__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #if defined(__sparclite__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* This has hardware multiply but not divide. It also has two additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) instructions scan (ffs from high bit) and divscc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) __asm__ ("umul %2,%3,%1;rd %%y,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) : "=r" ((USItype)(w1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "=r" ((USItype)(w0)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) : "r" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "r" ((USItype)(v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define UMUL_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) __asm__ ("! Inlined udiv_qrnnd\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "tst %%g0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "divscc %3,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) "divscc %%g1,%4,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "divscc %%g1,%4,%0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) "rd %%y,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) "bl,a 1f\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "add %1,%4,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "1: ! End of inline udiv_qrnnd" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) : "=r" ((USItype)(q)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "=r" ((USItype)(r)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) : "r" ((USItype)(n1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "r" ((USItype)(n0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "rI" ((USItype)(d)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) : "%g1" __AND_CLOBBER_CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define UDIV_TIME 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #endif /* __sparclite__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #endif /* __sparc_v8__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #ifndef umul_ppmm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) __asm__ ("! Inlined umul_ppmm\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) "sra %3,31,%%g2 ! Don't move this insn\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) "and %2,%%g2,%%g2 ! Don't move this insn\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) "andcc %%g0,0,%%g1 ! Don't move this insn\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "mulscc %%g1,%3,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "mulscc %%g1,0,%%g1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) "add %%g1,%%g2,%0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "rd %%y,%1" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) : "=r" ((USItype)(w1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) "=r" ((USItype)(w0)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) : "%rI" ((USItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "r" ((USItype)(v)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) : "%g1", "%g2" __AND_CLOBBER_CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define UMUL_TIME 39 /* 39 instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* It's quite necessary to add this much assembler for the sparc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) The default udiv_qrnnd (in C) is more than 10 times slower! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) __asm__ ("! Inlined udiv_qrnnd\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) "mov 32,%%g1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "subcc %1,%2,%%g0\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "1: bcs 5f\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "sub %1,%2,%1 ! this kills msb of n\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "addx %1,%1,%1 ! so this can't give carry\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) "subcc %%g1,1,%%g1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) "2: bne 1b\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) "subcc %1,%2,%%g0\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) "bcs 3f\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) "b 3f\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) "sub %1,%2,%1 ! this kills msb of n\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "4: sub %1,%2,%1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) "5: addxcc %1,%1,%1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "bcc 2b\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "subcc %%g1,1,%%g1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "! Got carry from n. Subtract next step to cancel this carry.\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "bne 4b\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) "sub %1,%2,%1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "3: xnor %0,0,%0\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) "! End of inline udiv_qrnnd\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) : "=&r" ((USItype)(q)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) "=&r" ((USItype)(r)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) : "r" ((USItype)(d)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) "1" ((USItype)(n1)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "0" ((USItype)(n0)) : "%g1", "cc")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #endif /* __sparc__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ************** VAX ******************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #if defined(__vax__) && W_TYPE_SIZE == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) __asm__ ("addl2 %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "adwc %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) : "=g" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "=&g" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) : "%0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "%1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) __asm__ ("subl2 %5,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) "sbwc %3,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) : "=g" ((USItype)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "=&g" ((USItype)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) : "0" ((USItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) "g" ((USItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "1" ((USItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) "g" ((USItype)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define umul_ppmm(xh, xl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) union {UDItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct {USItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) USItype __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) __asm__ ("emul %1,%2,$0,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) : "=g" (__xx.__ll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) : "g" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) "g" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) (xh) += ((((SItype) __m0 >> 31) & __m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) + (((SItype) __m1 >> 31) & __m0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define sdiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) union {DItype __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct {SItype __l, __h; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) __xx.__i.__h = n1; __xx.__i.__l = n0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) __asm__ ("ediv %3,%2,%0,%1" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) : "=g" (q), "=g" (r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) : "g" (__xx.__ll), "g" (d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #endif /* __vax__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ************** Z8000 ****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #if defined(__z8000__) && W_TYPE_SIZE == 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) : "=r" ((unsigned int)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "=&r" ((unsigned int)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) : "%0" ((unsigned int)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "r" ((unsigned int)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "%1" ((unsigned int)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) "rQR" ((unsigned int)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) : "=r" ((unsigned int)(sh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) "=&r" ((unsigned int)(sl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) : "0" ((unsigned int)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "r" ((unsigned int)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) "1" ((unsigned int)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) "rQR" ((unsigned int)(bl)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define umul_ppmm(xh, xl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) union {long int __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct {unsigned int __h, __l; } __i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) } __xx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) unsigned int __m0 = (m0), __m1 = (m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) __asm__ ("mult %S0,%H3" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) : "=r" (__xx.__i.__h), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) "=r" (__xx.__i.__l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) : "%1" (__m0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) "rQR" (__m1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) (xh) += ((((signed int) __m0 >> 15) & __m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) + (((signed int) __m1 >> 15) & __m0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #endif /* __z8000__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #endif /* __GNUC__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) *********** Generic Versions ********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #if !defined(umul_ppmm) && defined(__umulsidi3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define umul_ppmm(ph, pl, m0, m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) UDWtype __ll = __umulsidi3(m0, m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ph = (UWtype) (__ll >> W_TYPE_SIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) pl = (UWtype) __ll; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #if !defined(__umulsidi3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define __umulsidi3(u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ({UWtype __hi, __lo; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) umul_ppmm(__hi, __lo, u, v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ((UDWtype) __hi << W_TYPE_SIZE) | __lo; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* If this machine has no inline assembler, use C macros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #if !defined(add_ssaaaa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) UWtype __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) __x = (al) + (bl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) (sh) = (ah) + (bh) + (__x < (al)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) (sl) = __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #if !defined(sub_ddmmss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) UWtype __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) __x = (al) - (bl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) (sh) = (ah) - (bh) - (__x > (al)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) (sl) = __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #if !defined(umul_ppmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) UWtype __x0, __x1, __x2, __x3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) UHWtype __ul, __vl, __uh, __vh; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) UWtype __u = (u), __v = (v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) __ul = __ll_lowpart(__u); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) __uh = __ll_highpart(__u); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) __vl = __ll_lowpart(__v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) __vh = __ll_highpart(__v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) __x0 = (UWtype) __ul * __vl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) __x1 = (UWtype) __ul * __vh; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) __x2 = (UWtype) __uh * __vl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) __x3 = (UWtype) __uh * __vh; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) __x1 += __ll_highpart(__x0);/* this can't give carry */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) __x1 += __x2; /* but this indeed can */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (__x1 < __x2) /* did we get it? */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) __x3 += __ll_B; /* yes, add it in the proper pos. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) (w1) = __x3 + __ll_highpart(__x1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) (w0) = (__ll_lowpart(__x1) << W_TYPE_SIZE/2) + __ll_lowpart(__x0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #if !defined(umul_ppmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define smul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) UWtype __w1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) UWtype __m0 = (u), __m1 = (v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) umul_ppmm(__w1, w0, __m0, __m1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) (w1) = __w1 - (-(__m0 >> (W_TYPE_SIZE - 1)) & __m1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) - (-(__m1 >> (W_TYPE_SIZE - 1)) & __m0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* Define this unconditionally, so it can be used for debugging. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define __udiv_qrnnd_c(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) __d1 = __ll_highpart(d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) __d0 = __ll_lowpart(d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) __r1 = (n1) % __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) __q1 = (n1) / __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) __m = (UWtype) __q1 * __d0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) __r1 = __r1 * __ll_B | __ll_highpart(n0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (__r1 < __m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) __q1--, __r1 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (__r1 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) __q1--, __r1 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) __r1 -= __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) __r0 = __r1 % __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) __q0 = __r1 / __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) __m = (UWtype) __q0 * __d0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) __r0 = __r0 * __ll_B | __ll_lowpart(n0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (__r0 < __m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) __q0--, __r0 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (__r0 >= (d)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (__r0 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) __q0--, __r0 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) __r0 -= __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) (q) = (UWtype) __q1 * __ll_B | __q0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) (r) = __r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) __udiv_w_sdiv (defined in libgcc or elsewhere). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #if !defined(udiv_qrnnd) && defined(sdiv_qrnnd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define udiv_qrnnd(q, r, nh, nl, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) UWtype __r; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) (q) = __MPN(udiv_w_sdiv) (&__r, nh, nl, d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) (r) = __r; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #if !defined(udiv_qrnnd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define UDIV_NEEDS_NORMALIZATION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define udiv_qrnnd __udiv_qrnnd_c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #ifndef UDIV_NEEDS_NORMALIZATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define UDIV_NEEDS_NORMALIZATION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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