Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Jiang Liu <jiang.liu@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is licensed under GPLv2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file contains common code to support Message Signalled Interrupt for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * PCI compatible and non PCI compatible devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "internals.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * alloc_msi_entry - Allocate an initialize msi_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * @dev:	Pointer to the device for which this is allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * @nvec:	The number of vectors used in this entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * @affinity:	Optional pointer to an affinity mask array size of @nvec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * If @affinity is not NULL then an affinity array[@nvec] is allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * and the affinity masks and flags from @affinity are copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				 const struct irq_affinity_desc *affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	INIT_LIST_HEAD(&desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	desc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	desc->nvec_used = nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (affinity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		desc->affinity = kmemdup(affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			nvec * sizeof(*desc->affinity), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		if (!desc->affinity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) void free_msi_entry(struct msi_desc *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	kfree(entry->affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	kfree(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	*msg = entry->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct msi_desc *entry = irq_get_msi_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__get_cached_msi_msg(entry, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) EXPORT_SYMBOL_GPL(get_cached_msi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static inline void irq_chip_write_msi_msg(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					  struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	data->chip->irq_write_msi_msg(data, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void msi_check_level(struct irq_domain *domain, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * If the MSI provider has messed with the second message and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * not advertized that it is level-capable, signal the breakage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		  (info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		(msg[1].address_lo || msg[1].address_hi || msg[1].data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * msi_domain_set_affinity - Generic affinity setter function for MSI domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * @irq_data:	The irq data associated to the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * @mask:	The affinity mask to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * @force:	Flag to enforce setting (disable online checks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * Intended to be used by MSI interrupt controllers which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * implemented with hierarchical domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int msi_domain_set_affinity(struct irq_data *irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			    const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct irq_data *parent = irq_data->parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct msi_msg msg[2] = { [1] = { }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	ret = parent->chip->irq_set_affinity(parent, mask, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		msi_check_level(irq_data->domain, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		irq_chip_write_msi_msg(irq_data, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int msi_domain_activate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			       struct irq_data *irq_data, bool early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct msi_msg msg[2] = { [1] = { }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	msi_check_level(irq_data->domain, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	irq_chip_write_msi_msg(irq_data, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void msi_domain_deactivate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				  struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct msi_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	memset(msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	irq_chip_write_msi_msg(irq_data, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			    unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (irq_find_mapping(domain, hwirq) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (domain->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			if (ops->msi_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				for (i--; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					ops->msi_free(domain, info, virq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			irq_domain_free_irqs_top(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			    unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (info->ops->msi_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			info->ops->msi_free(domain, info, virq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	irq_domain_free_irqs_top(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct irq_domain_ops msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.alloc		= msi_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.free		= msi_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.activate	= msi_domain_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.deactivate	= msi_domain_deactivate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 						msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return arg->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				  int nvec, msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	memset(arg, 0, sizeof(*arg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				    struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	arg->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int msi_domain_ops_init(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			       struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			       unsigned int virq, irq_hw_number_t hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			       msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				      info->chip_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (info->handler && info->handler_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		__irq_set_handler(virq, info->handler, 0, info->handler_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (info->handler_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			irq_set_handler_data(virq, info->handler_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int msi_domain_ops_check(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct msi_domain_ops msi_domain_ops_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.get_hwirq		= msi_domain_ops_get_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.msi_init		= msi_domain_ops_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.msi_check		= msi_domain_ops_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.msi_prepare		= msi_domain_ops_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.set_desc		= msi_domain_ops_set_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.domain_alloc_irqs	= __msi_domain_alloc_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.domain_free_irqs	= __msi_domain_free_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void msi_domain_update_dom_ops(struct msi_domain_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ops == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		info->ops = &msi_domain_ops_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (ops->domain_alloc_irqs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		ops->domain_alloc_irqs = msi_domain_ops_default.domain_alloc_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ops->domain_free_irqs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		ops->domain_free_irqs = msi_domain_ops_default.domain_free_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!(info->flags & MSI_FLAG_USE_DEF_DOM_OPS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (ops->get_hwirq == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ops->get_hwirq = msi_domain_ops_default.get_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (ops->msi_init == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ops->msi_init = msi_domain_ops_default.msi_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ops->msi_check == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		ops->msi_check = msi_domain_ops_default.msi_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (ops->msi_prepare == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		ops->msi_prepare = msi_domain_ops_default.msi_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (ops->set_desc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		ops->set_desc = msi_domain_ops_default.set_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void msi_domain_update_chip_ops(struct msi_domain_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct irq_chip *chip = info->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (!chip->irq_set_affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		chip->irq_set_affinity = msi_domain_set_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * msi_create_irq_domain - Create a MSI interrupt domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * @fwnode:	Optional fwnode of the interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * @info:	MSI domain info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * @parent:	Parent irq domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 					 struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 					 struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	msi_domain_update_dom_ops(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		msi_domain_update_chip_ops(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 					     fwnode, &msi_domain_ops, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (domain && !domain->name && info->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		domain->name = info->chip->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			    int nvec, msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ret = ops->msi_check(domain, info, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		ret = ops->msi_prepare(domain, dev, nvec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			     int virq, int nvec, msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	for_each_msi_entry(desc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		/* Don't even try the multi-MSI brain damage. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		ops->set_desc(arg, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		/* Assumes the domain mutex is held! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		ret = irq_domain_alloc_irqs_hierarchy(domain, desc->irq, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 						      arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		irq_set_msi_desc_off(desc->irq, 0, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		/* Mop up the damage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		for_each_msi_entry(desc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			irq_domain_free_irqs_common(domain, desc->irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  * Carefully check whether the device can use reservation mode. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  * reservation mode is enabled then the early activation will assign a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  * dummy vector to the device. If the PCI/MSI device does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  * masking of the entry then this can result in spurious interrupts when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  * the device driver is not absolutely careful. But even then a malfunction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * of the hardware could result in a spurious interrupt on the dummy vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  * and render the device unusable. If the entry can be masked then the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  * logic will prevent the spurious interrupt and reservation mode can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  * used. For now reservation mode is restricted to PCI/MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static bool msi_check_reservation_mode(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				       struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 				       struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	switch(domain->bus_token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	case DOMAIN_BUS_PCI_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	case DOMAIN_BUS_VMD_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	 * Checking the first MSI descriptor is sufficient. MSIX supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	 * masking and MSI does so when the maskbit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	desc = first_msi_entry(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 			    int nvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	msi_alloc_info_t arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	int i, ret, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	bool can_reserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	for_each_msi_entry(desc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		ops->set_desc(&arg, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 					       dev_to_node(dev), &arg, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 					       desc->affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		if (virq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			if (ops->handle_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 				ret = ops->handle_error(domain, desc, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			if (ops->msi_finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 				ops->msi_finish(&arg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		for (i = 0; i < desc->nvec_used; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			irq_set_msi_desc_off(virq, i, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			irq_debugfs_copy_devname(virq + i, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (ops->msi_finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		ops->msi_finish(&arg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	can_reserve = msi_check_reservation_mode(domain, info, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	 * This flag is set by the PCI layer as we need to activate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	 * the MSI entries before the PCI layer enables MSI in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	 * card. Otherwise the card latches a random msi message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		goto skip_activate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	for_each_msi_vector(desc, i, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		if (desc->irq == i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			virq = desc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			dev_dbg(dev, "irq [%d-%d] for MSI\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 				virq, virq + desc->nvec_used - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		irq_data = irq_domain_get_irq_data(domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		if (!can_reserve) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			irqd_clr_can_reserve(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 				irqd_set_msi_nomask_quirk(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		ret = irq_domain_activate_irq(irq_data, can_reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 			goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) skip_activate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	 * If these interrupts use reservation mode, clear the activated bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	 * so request_irq() will assign the final vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	if (can_reserve) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		for_each_msi_vector(desc, i, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			irq_data = irq_domain_get_irq_data(domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 			irqd_clr_activated(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	msi_domain_free_irqs(domain, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)  * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)  * @domain:	The domain to allocate from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)  * @dev:	Pointer to device struct of the device for which the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)  *		are allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)  * @nvec:	The number of interrupts to allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)  * Returns 0 on success or an error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 			  int nvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	return ops->domain_alloc_irqs(domain, dev, nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) void __msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	for_each_msi_vector(desc, i, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		irq_data = irq_domain_get_irq_data(domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		if (irqd_is_activated(irq_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 			irq_domain_deactivate_irq(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	for_each_msi_entry(desc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		 * We might have failed to allocate an MSI early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		 * enough that there is no IRQ associated to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		 * entry. If that's the case, don't do anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		if (desc->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 			irq_domain_free_irqs(desc->irq, desc->nvec_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 			desc->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)  * __msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)  * @domain:	The domain to managing the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)  * @dev:	Pointer to device struct of the device for which the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)  *		are free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	struct msi_domain_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	return ops->domain_free_irqs(domain, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)  * msi_get_domain_info - Get the MSI interrupt domain info for @domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)  * @domain:	The interrupt domain to retrieve data from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)  * Returns the pointer to the msi_domain_info stored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)  * @domain->host_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	return (struct msi_domain_info *)domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */