Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017-2018 Bartosz Golaszewski <brgl@bgdev.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2020 Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irq_sim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/irq_work.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) struct irq_sim_work_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	struct irq_work		work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	int			irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	unsigned int		irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	unsigned long		*pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	struct irq_domain	*domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct irq_sim_irq_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int			irqnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	bool			enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct irq_sim_work_ctx	*work_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct irq_sim_devres {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct irq_domain	*domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static void irq_sim_irqmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct irq_sim_irq_ctx *irq_ctx = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	irq_ctx->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static void irq_sim_irqunmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct irq_sim_irq_ctx *irq_ctx = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	irq_ctx->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int irq_sim_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* We only support rising and falling edge trigger types. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (type & ~IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	irqd_set_trigger_type(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int irq_sim_get_irqchip_state(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				     enum irqchip_irq_state which, bool *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct irq_sim_irq_ctx *irq_ctx = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	irq_hw_number_t hwirq = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case IRQCHIP_STATE_PENDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		if (irq_ctx->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			*state = test_bit(hwirq, irq_ctx->work_ctx->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int irq_sim_set_irqchip_state(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				     enum irqchip_irq_state which, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct irq_sim_irq_ctx *irq_ctx = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	irq_hw_number_t hwirq = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	case IRQCHIP_STATE_PENDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (irq_ctx->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			assign_bit(hwirq, irq_ctx->work_ctx->pending, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				irq_work_queue(&irq_ctx->work_ctx->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static struct irq_chip irq_sim_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.name			= "irq_sim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.irq_mask		= irq_sim_irqmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.irq_unmask		= irq_sim_irqunmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.irq_set_type		= irq_sim_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.irq_get_irqchip_state	= irq_sim_get_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.irq_set_irqchip_state	= irq_sim_set_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void irq_sim_handle_irq(struct irq_work *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct irq_sim_work_ctx *work_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int irqnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	work_ctx = container_of(work, struct irq_sim_work_ctx, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	while (!bitmap_empty(work_ctx->pending, work_ctx->irq_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		offset = find_next_bit(work_ctx->pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				       work_ctx->irq_count, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		clear_bit(offset, work_ctx->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		irqnum = irq_find_mapping(work_ctx->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		handle_simple_irq(irq_to_desc(irqnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int irq_sim_domain_map(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			      unsigned int virq, irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct irq_sim_work_ctx *work_ctx = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct irq_sim_irq_ctx *irq_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	irq_ctx = kzalloc(sizeof(*irq_ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (!irq_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	irq_set_chip(virq, &irq_sim_irqchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	irq_set_chip_data(virq, irq_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	irq_set_handler(virq, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	irq_modify_status(virq, IRQ_NOREQUEST | IRQ_NOAUTOEN, IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	irq_ctx->work_ctx = work_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void irq_sim_domain_unmap(struct irq_domain *domain, unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct irq_sim_irq_ctx *irq_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct irq_data *irqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	irqd = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	irq_ctx = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	irq_set_handler(virq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	irq_domain_reset_irq_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	kfree(irq_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct irq_domain_ops irq_sim_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.map		= irq_sim_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.unmap		= irq_sim_domain_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * irq_domain_create_sim - Create a new interrupt simulator irq_domain and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  *                         allocate a range of dummy interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * @fnode:      struct fwnode_handle to be associated with this domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * @num_irqs:   Number of interrupts to allocate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * On success: return a new irq_domain object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * On failure: a negative errno wrapped with ERR_PTR().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct irq_domain *irq_domain_create_sim(struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					 unsigned int num_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct irq_sim_work_ctx *work_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	work_ctx = kmalloc(sizeof(*work_ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!work_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	work_ctx->pending = bitmap_zalloc(num_irqs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (!work_ctx->pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		goto err_free_work_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	work_ctx->domain = irq_domain_create_linear(fwnode, num_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 						    &irq_sim_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 						    work_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!work_ctx->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		goto err_free_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	work_ctx->irq_count = num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	init_irq_work(&work_ctx->work, irq_sim_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return work_ctx->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err_free_bitmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	bitmap_free(work_ctx->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err_free_work_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	kfree(work_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) EXPORT_SYMBOL_GPL(irq_domain_create_sim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * irq_domain_remove_sim - Deinitialize the interrupt simulator domain: free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  *                         the interrupt descriptors and allocated memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * @domain:     The interrupt simulator domain to tear down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void irq_domain_remove_sim(struct irq_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct irq_sim_work_ctx *work_ctx = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	irq_work_sync(&work_ctx->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	bitmap_free(work_ctx->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	kfree(work_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) EXPORT_SYMBOL_GPL(irq_domain_remove_sim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void devm_irq_domain_release_sim(struct device *dev, void *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct irq_sim_devres *this = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	irq_domain_remove_sim(this->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * devm_irq_domain_create_sim - Create a new interrupt simulator for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  *                              a managed device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * @dev:        Device to initialize the simulator object for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * @fnode:      struct fwnode_handle to be associated with this domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * @num_irqs:   Number of interrupts to allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * On success: return a new irq_domain object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * On failure: a negative errno wrapped with ERR_PTR().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct irq_domain *devm_irq_domain_create_sim(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 					      struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					      unsigned int num_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct irq_sim_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	dr = devres_alloc(devm_irq_domain_release_sim,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			  sizeof(*dr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	dr->domain = irq_domain_create_sim(fwnode, num_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (IS_ERR(dr->domain)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		devres_free(dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return dr->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	devres_add(dev, dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return dr->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EXPORT_SYMBOL_GPL(devm_irq_domain_create_sim);