^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018-2020 Christoph Hellwig.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * DMA operations that map physical memory directly without using an IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/memblock.h> /* for max_pfn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pfn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/set_memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "direct.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * it for entirely different regions. In that case the arch code needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * override the variable below for dma-direct to work properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int zone_dma_bits __ro_after_init = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline dma_addr_t phys_to_dma_direct(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) phys_addr_t phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (force_dma_unencrypted(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return phys_to_dma_unencrypted(dev, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return phys_to_dma(dev, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline struct page *dma_direct_to_page(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u64 dma_direct_get_required_mask(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u64 max_dma = phys_to_dma_direct(dev, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) EXPORT_SYMBOL_GPL(dma_direct_get_required_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u64 *phys_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Optimistically try the zone that the physical address mask falls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * into first. If that returns memory that isn't actually addressable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * we will fallback to the next lower zone and try again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * zones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *phys_limit = dma_to_phys(dev, dma_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return GFP_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (*phys_limit <= DMA_BIT_MASK(32) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) !zone_dma32_are_empty())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return GFP_DMA32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (dma_addr == DMA_MAPPING_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return dma_addr + size - 1 <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int node = dev_to_node(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct page *page = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u64 phys_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) WARN_ON_ONCE(!PAGE_ALIGNED(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) &phys_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) page = dma_alloc_contiguous(dev, size, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dma_free_contiguous(dev, page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) page = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) page = alloc_pages_node(node, gfp, get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma_free_contiguous(dev, page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) page = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) phys_limit < DMA_BIT_MASK(64) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) !(gfp & (GFP_DMA32 | GFP_DMA)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) !zone_dma32_are_empty()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) gfp |= GFP_DMA32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dma_addr_t *dma_handle, gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u64 phys_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &phys_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void *dma_direct_alloc(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) size = PAGE_ALIGN(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (attrs & DMA_ATTR_NO_WARN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) gfp |= __GFP_NOWARN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) !force_dma_unencrypted(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* remove any dirty cache lines on the kernel alias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!PageHighMem(page))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) arch_dma_prep_coherent(page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* return the page pointer as the opaque cookie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) !dev_is_dma_coherent(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Remapping or decrypting memory may block. If either is required and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * we can't block, allocate the memory from the atomic pools.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) !gfpflags_allow_blocking(gfp) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (force_dma_unencrypted(dev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* we always manually zero the memory once we are done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) !dev_is_dma_coherent(dev)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* remove any dirty cache lines on the kernel alias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) arch_dma_prep_coherent(page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* create a coherent mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = dma_common_contiguous_remap(page, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dma_pgprot(dev, PAGE_KERNEL, attrs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __builtin_return_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto out_free_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (force_dma_unencrypted(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) err = set_memory_decrypted((unsigned long)ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 1 << get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto out_free_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) memset(ret, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (PageHighMem(page)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Depending on the cma= arguments and per-arch setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * dma_alloc_contiguous could return highmem pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Without remapping there is no way to return them here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * so log an error and fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_info(dev, "Rejecting highmem page from CMA.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto out_free_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = page_address(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (force_dma_unencrypted(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) err = set_memory_decrypted((unsigned long)ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 1 << get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto out_free_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) memset(ret, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) !dev_is_dma_coherent(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) arch_dma_prep_coherent(page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = arch_dma_set_uncached(ret, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (IS_ERR(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto out_encrypt_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) out_encrypt_pages:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (force_dma_unencrypted(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err = set_memory_encrypted((unsigned long)page_address(page),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 1 << get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* If memory cannot be re-encrypted, it must be leaked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) out_free_pages:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dma_free_contiguous(dev, page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void dma_direct_free(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int page_order = get_order(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) !force_dma_unencrypted(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* cpu_addr is a struct page cookie, not a kernel address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dma_free_contiguous(dev, cpu_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) !dev_is_dma_coherent(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (force_dma_unencrypted(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) vunmap(cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) arch_dma_clear_uncached(cpu_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) page = __dma_direct_alloc_pages(dev, size, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (PageHighMem(page)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Depending on the cma= arguments and per-arch setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * dma_alloc_contiguous could return highmem pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Without remapping there is no way to return them here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * so log an error and fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_info(dev, "Rejecting highmem page from CMA.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto out_free_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = page_address(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (force_dma_unencrypted(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (set_memory_decrypted((unsigned long)ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 1 << get_order(size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto out_free_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) memset(ret, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) out_free_pages:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dma_free_contiguous(dev, page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) EXPORT_SYMBOL_GPL(dma_direct_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void dma_direct_free_pages(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct page *page, dma_addr_t dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int page_order = get_order(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void *vaddr = page_address(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dma_free_from_pool(dev, vaddr, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (force_dma_unencrypted(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) set_memory_encrypted((unsigned long)vaddr, 1 << page_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dma_free_contiguous(dev, page, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) EXPORT_SYMBOL_GPL(dma_direct_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) defined(CONFIG_SWIOTLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void dma_direct_sync_sg_for_device(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct scatterlist *sgl, int nents, enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for_each_sg(sgl, sg, nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (unlikely(is_swiotlb_buffer(paddr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) swiotlb_tbl_sync_single(dev, paddr, sg->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dir, SYNC_FOR_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!dev_is_dma_coherent(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) arch_sync_dma_for_device(paddr, sg->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) defined(CONFIG_SWIOTLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void dma_direct_sync_sg_for_cpu(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct scatterlist *sgl, int nents, enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for_each_sg(sgl, sg, nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!dev_is_dma_coherent(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) arch_sync_dma_for_cpu(paddr, sg->length, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (unlikely(is_swiotlb_buffer(paddr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SYNC_FOR_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (dir == DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) arch_dma_mark_clean(paddr, sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!dev_is_dma_coherent(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) arch_sync_dma_for_cpu_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int nents, enum dma_data_direction dir, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for_each_sg(sgl, sg, nents, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) enum dma_data_direction dir, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for_each_sg(sgl, sg, nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sg->offset, sg->length, dir, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (sg->dma_address == DMA_MAPPING_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) sg_dma_len(sg) = sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) size_t size, enum dma_data_direction dir, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dma_addr_t dma_addr = paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err_once(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return DMA_MAPPING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void *cpu_addr, dma_addr_t dma_addr, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct page *page = dma_direct_to_page(dev, dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) bool dma_direct_can_mmap(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return dev_is_dma_coherent(dev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) void *cpu_addr, dma_addr_t dma_addr, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long user_count = vma_pages(vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) user_count << PAGE_SHIFT, vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int dma_direct_supported(struct device *dev, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Because 32-bit DMA masks are so common we expect every architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * to be able to satisfy them - either by not supporting more physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * memory, or by providing a ZONE_DMA32. If neither is the case, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * architecture needs to use an IOMMU instead of the direct mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (mask >= DMA_BIT_MASK(32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * This check needs to be against the actual bit mask value, so use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * part of the check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (IS_ENABLED(CONFIG_ZONE_DMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return mask >= phys_to_dma_unencrypted(dev, min_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) size_t dma_direct_max_mapping_size(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* If SWIOTLB is active, use its maximum mapping size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (is_swiotlb_active() &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return swiotlb_max_mapping_size(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return !dev_is_dma_coherent(dev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * dma_direct_set_offset - Assign scalar offset for a single DMA range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @dev: device pointer; needed to "own" the alloced memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * @cpu_start: beginning of memory region covered by this offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * @dma_start: beginning of DMA/PCI region covered by this offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * @size: size of the region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * This is for the simple case of a uniform offset which cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * be discovered by "dma-ranges".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * It returns -ENOMEM if out of memory, -EINVAL if a map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * already exists, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Note: any call to this from a driver is a bug. The mapping needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * to be described by the device tree or other firmware interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dma_addr_t dma_start, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct bus_dma_region *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u64 offset = (u64)cpu_start - (u64)dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (dev->dma_range_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(dev, "attempt to add DMA range to existing map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) map = kcalloc(2, sizeof(*map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) map[0].cpu_start = cpu_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) map[0].dma_start = dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) map[0].offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) map[0].size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev->dma_range_map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) EXPORT_SYMBOL_GPL(dma_direct_set_offset);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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