Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Permission is hereby granted, free of charge, to any person obtaining a copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * of this software and associated documentation files (the "Software"), to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * deal in the Software without restriction, including without limitation the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * sell copies of the Software, and to permit persons to whom the Software is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #ifndef __XEN_PUBLIC_PHYSDEV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define __XEN_PUBLIC_PHYSDEV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Prototype for this hypercall is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  int physdev_op(int cmd, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * @cmd	 == PHYSDEVOP_??? (physdev operation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * @args == Operation-specific extra arguments (NULL if none).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * Notify end-of-interrupt (EOI) for the specified IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @arg == pointer to physdev_eoi structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PHYSDEVOP_eoi			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct physdev_eoi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	uint32_t irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * Register a shared page for the hypervisor to indicate whether the guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * must issue PHYSDEVOP_eoi. The semantics of PHYSDEVOP_eoi change slightly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * once the guest used this function in that the associated event channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * will automatically get unmasked. The page registered is used as a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * array indexed by Xen's PIRQ value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PHYSDEVOP_pirq_eoi_gmfn_v1       17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Register a shared page for the hypervisor to indicate whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * guest must issue PHYSDEVOP_eoi. This hypercall is very similar to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * PHYSDEVOP_pirq_eoi_gmfn_v1 but it doesn't change the semantics of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * PHYSDEVOP_eoi. The page registered is used as a bit array indexed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * Xen's PIRQ value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PHYSDEVOP_pirq_eoi_gmfn_v2       28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct physdev_pirq_eoi_gmfn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)     xen_ulong_t gmfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * Query the status of an IRQ line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * @arg == pointer to physdev_irq_status_query structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PHYSDEVOP_irq_status_query	 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct physdev_irq_status_query {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	uint32_t irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	uint32_t flags; /* XENIRQSTAT_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Need to call PHYSDEVOP_eoi when the IRQ has been serviced? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define _XENIRQSTAT_needs_eoi	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define	 XENIRQSTAT_needs_eoi	(1U<<_XENIRQSTAT_needs_eoi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* IRQ shared by multiple guests? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define _XENIRQSTAT_shared	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define	 XENIRQSTAT_shared	(1U<<_XENIRQSTAT_shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * Set the current VCPU's I/O privilege level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * @arg == pointer to physdev_set_iopl structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PHYSDEVOP_set_iopl		 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct physdev_set_iopl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	uint32_t iopl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * Set the current VCPU's I/O-port permissions bitmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * @arg == pointer to physdev_set_iobitmap structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PHYSDEVOP_set_iobitmap		 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) struct physdev_set_iobitmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	uint8_t * bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	uint32_t nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * Read or write an IO-APIC register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * @arg == pointer to physdev_apic structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHYSDEVOP_apic_read		 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PHYSDEVOP_apic_write		 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct physdev_apic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned long apic_physbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* IN or OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * Allocate or free a physical upcall vector for the specified IRQ line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * @arg == pointer to physdev_irq structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PHYSDEVOP_alloc_irq_vector	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PHYSDEVOP_free_irq_vector	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct physdev_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	uint32_t irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* IN or OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	uint32_t vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MAP_PIRQ_TYPE_MSI		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MAP_PIRQ_TYPE_GSI		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAP_PIRQ_TYPE_UNKNOWN		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MAP_PIRQ_TYPE_MSI_SEG		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MAP_PIRQ_TYPE_MULTI_MSI		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PHYSDEVOP_map_pirq		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct physdev_map_pirq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)     domid_t domid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)     int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)     int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)     /* IN or OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)     int pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)     /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)     int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)     int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)     /* IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)      * - For MSI-X contains entry number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)      * - For MSI with ..._MULTI_MSI contains number of vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)      * OUT (..._MULTI_MSI only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)      * - Number of vectors allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)     int entry_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)     uint64_t table_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PHYSDEVOP_unmap_pirq		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct physdev_unmap_pirq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)     domid_t domid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)     int pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PHYSDEVOP_manage_pci_add	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PHYSDEVOP_manage_pci_remove	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct physdev_manage_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	uint8_t devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PHYSDEVOP_restore_msi            19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct physdev_restore_msi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	uint8_t devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PHYSDEVOP_manage_pci_add_ext	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct physdev_manage_pci_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	uint8_t devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	unsigned is_extfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	unsigned is_virtfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		uint8_t devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	} physfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * Argument to physdev_op_compat() hypercall. Superceded by new physdev_op()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * hypercall since 0x00030202.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct physdev_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	uint32_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		struct physdev_irq_status_query	     irq_status_query;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		struct physdev_set_iopl		     set_iopl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		struct physdev_set_iobitmap	     set_iobitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		struct physdev_apic		     apic_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		struct physdev_irq		     irq_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	} u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PHYSDEVOP_setup_gsi    21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct physdev_setup_gsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)     int gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)     uint8_t triggering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)     uint8_t polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PHYSDEVOP_get_nr_pirqs    22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct physdev_nr_pirqs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)     /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)     uint32_t nr_pirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* type is MAP_PIRQ_TYPE_GSI or MAP_PIRQ_TYPE_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * the hypercall returns a free pirq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PHYSDEVOP_get_free_pirq    23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct physdev_get_free_pirq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)     /* IN */ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)     int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)     /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)     uint32_t pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define XEN_PCI_DEV_EXTFN              0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define XEN_PCI_DEV_VIRTFN             0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define XEN_PCI_DEV_PXM                0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define XEN_PCI_MMCFG_RESERVED         0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PHYSDEVOP_pci_mmcfg_reserved    24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct physdev_pci_mmcfg_reserved {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)     uint64_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)     uint16_t segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)     uint8_t start_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)     uint8_t end_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)     uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PHYSDEVOP_pci_device_add        25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct physdev_pci_device_add {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)     uint16_t seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)     uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)     uint8_t devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)     uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)     struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)         uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)         uint8_t devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)     } physfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)     uint32_t optarr[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #elif defined(__GNUC__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)     uint32_t optarr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PHYSDEVOP_pci_device_remove     26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PHYSDEVOP_restore_msi_ext       27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * Dom0 should use these two to announce MMIO resources assigned to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * MSI-X capable devices won't (prepare) or may (release) change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PHYSDEVOP_prepare_msix          30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PHYSDEVOP_release_msix          31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct physdev_pci_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)     uint16_t seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)     uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)     uint8_t devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PHYSDEVOP_DBGP_RESET_PREPARE    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PHYSDEVOP_DBGP_RESET_DONE       2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PHYSDEVOP_DBGP_BUS_UNKNOWN      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PHYSDEVOP_DBGP_BUS_PCI          1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PHYSDEVOP_dbgp_op               29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct physdev_dbgp_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)     /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)     uint8_t op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)     uint8_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)     union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)         struct physdev_pci_device pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)     } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  * Notify that some PIRQ-bound event channels have been unmasked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * ** This command is obsolete since interface version 0x00030202 and is **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  * ** unsupported by newer versions of Xen.				 **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define PHYSDEVOP_IRQ_UNMASK_NOTIFY	 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * These all-capitals physdev operation names are superceded by the new names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  * (defined above) since interface version 0x00030202.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PHYSDEVOP_IRQ_STATUS_QUERY	 PHYSDEVOP_irq_status_query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PHYSDEVOP_SET_IOPL		 PHYSDEVOP_set_iopl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PHYSDEVOP_SET_IOBITMAP		 PHYSDEVOP_set_iobitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PHYSDEVOP_APIC_READ		 PHYSDEVOP_apic_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PHYSDEVOP_APIC_WRITE		 PHYSDEVOP_apic_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PHYSDEVOP_ASSIGN_VECTOR		 PHYSDEVOP_alloc_irq_vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PHYSDEVOP_FREE_VECTOR		 PHYSDEVOP_free_irq_vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PHYSDEVOP_IRQ_SHARED		 XENIRQSTAT_shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif /* __XEN_PUBLIC_PHYSDEV_H__ */