^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Permission is hereby granted, free of charge, to any person obtaining a copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * of this software and associated documentation files (the "Software"), to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * deal in the Software without restriction, including without limitation the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * sell copies of the Software, and to permit persons to whom the Software is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef __XEN_PUBLIC_HVM_PARAMS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define __XEN_PUBLIC_HVM_PARAMS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <xen/interface/hvm/hvm_op.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Parameter space for HVMOP_{set,get}_param.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HVM_PARAM_CALLBACK_IRQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * How should CPU0 event-channel notifications be delivered?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * If val == 0 then CPU0 event-channel notifications are not delivered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * If val != 0, val[63:56] encodes the type, as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HVM_PARAM_CALLBACK_TYPE_GSI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * and disables all notifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * val[55:0] is a delivery PCI INTx line:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #if defined(__i386__) || defined(__x86_64__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * if this delivery method is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #elif defined(__arm__) || defined(__aarch64__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HVM_PARAM_CALLBACK_TYPE_PPI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * val[55:16] needs to be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * val[15:8] is interrupt flag of the PPI used by event-channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * bit 8: the PPI is edge(1) or level(0) triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * bit 9: the PPI is active low(1) or high(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * val[7:0] is a PPI number used by event-channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * the notification is handled by the interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HVM_PARAM_STORE_PFN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HVM_PARAM_STORE_EVTCHN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HVM_PARAM_PAE_ENABLED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HVM_PARAM_IOREQ_PFN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HVM_PARAM_BUFIOREQ_PFN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Set mode for virtual timers (currently x86 only):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * delay_for_missed_ticks (default):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Do not advance a vcpu's time beyond the correct delivery time for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * interrupts that have been missed due to preemption. Deliver missed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * interrupts when the vcpu is rescheduled and advance the vcpu's virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * time stepwise for each one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * no_delay_for_missed_ticks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * As above, missed interrupts are delivered, but guest time always tracks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * wallclock (i.e., real) time while doing so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * no_missed_ticks_pending:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * No missed interrupts are held pending. Instead, to ensure ticks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * delivered at some non-zero rate, if we detect missed ticks then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * internal tick alarm is not disabled if the VCPU is preempted during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * next tick period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * one_missed_tick_pending:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Missed interrupts are collapsed together and delivered as one 'late tick'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Guest time always tracks wallclock (i.e., real) time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HVM_PARAM_TIMER_MODE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HVMPTM_delay_for_missed_ticks 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HVMPTM_no_delay_for_missed_ticks 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HVMPTM_no_missed_ticks_pending 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HVMPTM_one_missed_tick_pending 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HVM_PARAM_HPET_ENABLED 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HVM_PARAM_IDENT_PT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Device Model domain, defaults to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HVM_PARAM_DM_DOMAIN 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* ACPI S state: currently support S0 and S3 on x86. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HVM_PARAM_ACPI_S_STATE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* TSS used on Intel when CR0.PE=0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HVM_PARAM_VM86_TSS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HVM_PARAM_VPT_ALIGN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Console debug shared memory ring and event channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HVM_PARAM_CONSOLE_PFN 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HVM_PARAM_CONSOLE_EVTCHN 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HVM_NR_PARAMS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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