^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for the w100 frame buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2004-2005 Richard Purdie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2005 Ian Molton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define W100_GPIO_PORT_A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define W100_GPIO_PORT_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_SRC_XTAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_SRC_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct w100fb_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned long w100fb_gpio_read(int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void w100fb_gpio_write(int port, unsigned long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned long w100fb_get_hsynclen(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* LCD Specific Routines and Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct w100_tg_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void (*change)(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void (*suspend)(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void (*resume)(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* General Platform Specific w100 Register Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct w100_gen_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long lcd_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long lcdd_cntl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long lcdd_cntl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long genlcd_cntl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long genlcd_cntl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long genlcd_cntl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct w100_gpio_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long init_data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long init_data2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long gpio_dir1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long gpio_oe1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long gpio_dir2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long gpio_oe2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Optional External Memory Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct w100_mem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long ext_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long sdram_mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long ext_timing_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long io_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct w100_bm_mem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long ext_mem_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long ext_timing_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long ext_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long io_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* LCD Mode definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct w100_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned short left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned short right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned short upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned short lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long crtc_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long crtc_ls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long crtc_gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long crtc_vpos_gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long crtc_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long crtc_dclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long crtc_gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long crtc_goe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long crtc_ps1_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) char pll_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) char fast_pll_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int sysclk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int sysclk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int pixclk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int pixclk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int pixclk_divider_rotated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct w100_pll_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) uint16_t freq; /* desired Fout for PLL (Mhz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) uint8_t M; /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) uint8_t N_int; /* VCO multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) uint8_t N_fac; /* VCO multiplier fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) uint8_t tfgoal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint8_t lock_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Initial Video mode orientation flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INIT_MODE_ROTATED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INIT_MODE_FLIPPED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * This structure describes the machine which we are running on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * It is set by machine specific code and used in the probe routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * of drivers/video/w100fb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct w100fb_mach_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* General Platform Specific Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct w100_gen_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Table of modes the LCD is capable of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct w100_mode *modelist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Hooks for any platform specific tg/lcd code (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct w100_tg_info *tg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* External memory definition (if present) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct w100_mem_info *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Additional External memory definition (if present) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct w100_bm_mem_info *bm_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* GPIO definitions (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct w100_gpio_regs *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Initial Mode flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int init_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Xtal Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Enable Xtal input doubler (1 == enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int xtal_dbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* General frame buffer data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct w100fb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int extmem_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int blanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int fastpll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct w100_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct w100_pll_info *pll_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct w100fb_mach_info *mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) uint32_t *saved_intmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) uint32_t *saved_extmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags