^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/include/video/vga.h -- standard VGA chipset interaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright history from vga16fb.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 1999 Ben Pfaff and Petr Vandrovec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on VESA framebuffer (c) 1998 Gerd Knorr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Public License. See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef __linux_video_vga_h__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __linux_video_vga_h__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Some of the code below is taken from SVGAlib. The original,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unmodified copyright notice for that code is below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* This library is free software; you can redistribute it and/or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* modify it without any restrictions. This library is distributed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* in the hope that it will be useful, but without any warranty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* partially copyrighted (C) 1993 by Hartmut Schirmer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* VGA data register ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VGA_PEL_D 0x3C9 /* PEL Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VGA_PEL_MSK 0x3C6 /* PEL mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* EGA-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* VGA index register ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VGA_GFX_I 0x3CE /* Graphics Controller Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VGA_SEQ_I 0x3C4 /* Sequencer Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VGA_PEL_IW 0x3C8 /* PEL Write Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VGA_PEL_IR 0x3C7 /* PEL Read Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* standard VGA indexes max counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VGA_MIS_C 0x01 /* Number of Misc Output Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* VGA misc register bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VGA_MIS_COLOR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VGA_MIS_ENB_MEM_ACCESS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VGA_MIS_DCLK_28322_720 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VGA_MIS_SEL_HIGH_PAGE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* VGA CRT controller register indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VGA_CRTC_H_TOTAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VGA_CRTC_H_DISP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VGA_CRTC_H_BLANK_START 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VGA_CRTC_H_BLANK_END 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VGA_CRTC_H_SYNC_START 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VGA_CRTC_H_SYNC_END 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VGA_CRTC_V_TOTAL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VGA_CRTC_OVERFLOW 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VGA_CRTC_PRESET_ROW 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VGA_CRTC_MAX_SCAN 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VGA_CRTC_CURSOR_START 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VGA_CRTC_CURSOR_END 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VGA_CRTC_START_HI 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VGA_CRTC_START_LO 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define VGA_CRTC_CURSOR_HI 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VGA_CRTC_CURSOR_LO 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VGA_CRTC_V_SYNC_START 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VGA_CRTC_V_SYNC_END 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VGA_CRTC_V_DISP_END 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VGA_CRTC_OFFSET 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VGA_CRTC_UNDERLINE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VGA_CRTC_V_BLANK_START 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VGA_CRTC_V_BLANK_END 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VGA_CRTC_MODE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VGA_CRTC_LINE_COMPARE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VGA_CRTC_REGS VGA_CRT_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* VGA CRT controller bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* VGA attribute controller register indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VGA_ATC_PALETTE0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VGA_ATC_PALETTE1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VGA_ATC_PALETTE2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VGA_ATC_PALETTE3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VGA_ATC_PALETTE4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VGA_ATC_PALETTE5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VGA_ATC_PALETTE6 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VGA_ATC_PALETTE7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VGA_ATC_PALETTE8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VGA_ATC_PALETTE9 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VGA_ATC_PALETTEA 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VGA_ATC_PALETTEB 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VGA_ATC_PALETTEC 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VGA_ATC_PALETTED 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VGA_ATC_PALETTEE 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VGA_ATC_PALETTEF 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VGA_ATC_MODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VGA_ATC_OVERSCAN 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VGA_ATC_PLANE_ENABLE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VGA_ATC_PEL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VGA_ATC_COLOR_PAGE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VGA_AR_ENABLE_DISPLAY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* VGA sequencer register indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VGA_SEQ_RESET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VGA_SEQ_CLOCK_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VGA_SEQ_PLANE_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VGA_SEQ_CHARACTER_MAP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VGA_SEQ_MEMORY_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* VGA sequencer register bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* VGA graphics controller register indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VGA_GFX_SR_VALUE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VGA_GFX_SR_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VGA_GFX_COMPARE_VALUE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VGA_GFX_DATA_ROTATE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VGA_GFX_PLANE_READ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VGA_GFX_MODE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VGA_GFX_MISC 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VGA_GFX_COMPARE_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VGA_GFX_BIT_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* VGA graphics controller bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VGA_GR06_GRAPHICS_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* macro for composing an 8-bit VGA register index and value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * into a single 16-bit quantity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VGA_OUT16VAL(v, r) (((v) << 8) | (r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* decide whether we should enable the faster 16-bit VGA register writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* VGA State Save and Restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VGA_SAVE_FONTS 7 /* save/restore all fonts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define VGA_SAVE_MODE 8 /* save/restore video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct vgastate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *vgabase; /* mmio base, if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long membase; /* VGA window base, 0 for default - 0xA000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __u32 memsize; /* VGA window size, 0 for default 64K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __u32 depth; /* current fb depth, not important */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __u32 num_attr; /* number of att registers, 0 for default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __u32 num_crtc; /* number of crt registers, 0 for default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __u32 num_gfx; /* number of gfx registers, 0 for default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __u32 num_seq; /* number of seq registers, 0 for default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void *vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) extern int save_vga(struct vgastate *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) extern int restore_vga(struct vgastate *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * generic VGA port read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline unsigned char vga_io_r (unsigned short port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return inb_p(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline void vga_io_w (unsigned short port, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) outb_p(val, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline void vga_io_w_fast (unsigned short port, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) outw(VGA_OUT16VAL (val, reg), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return readb (regbase + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writeb (val, regbase + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writew (VGA_OUT16VAL (val, reg), regbase + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline unsigned char vga_r (void __iomem *regbase, unsigned short port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return vga_mm_r (regbase, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return vga_io_r (port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) vga_mm_w (regbase, port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) vga_io_w (port, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline void vga_w_fast (void __iomem *regbase, unsigned short port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) vga_mm_w_fast (regbase, port, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) vga_io_w_fast (port, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * VGA CRTC register read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) vga_w (regbase, VGA_CRT_IC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return vga_r (regbase, VGA_CRT_DC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) vga_w_fast (regbase, VGA_CRT_IC, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) vga_w (regbase, VGA_CRT_IC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) vga_w (regbase, VGA_CRT_DC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static inline unsigned char vga_io_rcrt (unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) vga_io_w (VGA_CRT_IC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return vga_io_r (VGA_CRT_DC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static inline void vga_io_wcrt (unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) vga_io_w_fast (VGA_CRT_IC, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) vga_io_w (VGA_CRT_IC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) vga_io_w (VGA_CRT_DC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) vga_mm_w (regbase, VGA_CRT_IC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return vga_mm_r (regbase, VGA_CRT_DC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) vga_mm_w (regbase, VGA_CRT_IC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) vga_mm_w (regbase, VGA_CRT_DC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * VGA sequencer register read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) vga_w (regbase, VGA_SEQ_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return vga_r (regbase, VGA_SEQ_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) vga_w_fast (regbase, VGA_SEQ_I, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) vga_w (regbase, VGA_SEQ_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) vga_w (regbase, VGA_SEQ_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static inline unsigned char vga_io_rseq (unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) vga_io_w (VGA_SEQ_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return vga_io_r (VGA_SEQ_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static inline void vga_io_wseq (unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) vga_io_w_fast (VGA_SEQ_I, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) vga_io_w (VGA_SEQ_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vga_io_w (VGA_SEQ_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) vga_mm_w (regbase, VGA_SEQ_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return vga_mm_r (regbase, VGA_SEQ_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) vga_mm_w (regbase, VGA_SEQ_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) vga_mm_w (regbase, VGA_SEQ_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * VGA graphics controller register read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) vga_w (regbase, VGA_GFX_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return vga_r (regbase, VGA_GFX_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) vga_w_fast (regbase, VGA_GFX_I, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) vga_w (regbase, VGA_GFX_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) vga_w (regbase, VGA_GFX_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline unsigned char vga_io_rgfx (unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) vga_io_w (VGA_GFX_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return vga_io_r (VGA_GFX_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static inline void vga_io_wgfx (unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) vga_io_w_fast (VGA_GFX_I, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) vga_io_w (VGA_GFX_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) vga_io_w (VGA_GFX_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) vga_mm_w (regbase, VGA_GFX_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return vga_mm_r (regbase, VGA_GFX_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #ifdef VGA_OUTW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) vga_mm_w (regbase, VGA_GFX_I, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) vga_mm_w (regbase, VGA_GFX_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #endif /* VGA_OUTW_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * VGA attribute controller register read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) vga_w (regbase, VGA_ATT_IW, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return vga_r (regbase, VGA_ATT_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) vga_w (regbase, VGA_ATT_IW, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) vga_w (regbase, VGA_ATT_W, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline unsigned char vga_io_rattr (unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) vga_io_w (VGA_ATT_IW, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return vga_io_r (VGA_ATT_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static inline void vga_io_wattr (unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) vga_io_w (VGA_ATT_IW, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) vga_io_w (VGA_ATT_W, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) vga_mm_w (regbase, VGA_ATT_IW, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return vga_mm_r (regbase, VGA_ATT_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) vga_mm_w (regbase, VGA_ATT_IW, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) vga_mm_w (regbase, VGA_ATT_W, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #endif /* __linux_video_vga_h__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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