^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef TRIDENTFB_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define TRIDENTFB_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #if TRIDENTFB_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define debug(f, a...) printk("%s:" f, __func__ , ## a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define debug(f, a...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define output(f, a...) pr_info("tridentfb: " f, ## a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define Kb (1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define Mb (Kb*Kb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* PCI IDS of supported cards temporarily here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CYBER9320 0x9320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CYBER9388 0x9388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CYBER9385 0x9385 /* ditto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CYBER9397 0x9397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CYBER9397DVD 0x939A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CYBER9520 0x9520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CYBER9525DVD 0x9525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TGUI9440 0x9440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TGUI9660 0x9660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PROVIDIA9685 0x9685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMAGE975 0x9750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMAGE985 0x9850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BLADE3D 0x9880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CYBERBLADEE4 0x9540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CYBERBLADEi7 0x8400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CYBERBLADEi7D 0x8420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CYBERBLADEi1 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CYBERBLADEi1D 0x8520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CYBERBLADEAi1 0x8600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CYBERBLADEAi1D 0x8620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CYBERBLADEXPAi1 0x8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CYBERBLADEXPm8 0x9910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CYBERBLADEXPm16 0x9930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* these defines are for 'lcd' variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LCD_STRETCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LCD_CENTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LCD_BIOS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* General Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPR 0x1F /* Software Programming Register (videoram) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* 3C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RevisionID 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OldOrNew 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ConfPort1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ConfPort2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NewMode2 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NewMode1 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define Protection 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCLKLow 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCLKHigh 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ClockLow 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ClockHigh 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SSetup 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SKey 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPKey 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* 3x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CRTCModuleTest 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FIFOControl 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LinearAddReg 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRAMTiming 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define New32 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RAMDACTiming 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CRTHiOrd 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AddColReg 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define InterfaceSel 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HorizOverflow 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GETest 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define Performance 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GraphEngReg 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2C 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PixelBusReg 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCIReg 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DRAMControl 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MiscContReg 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CursorXLow 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CursorXHigh 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CursorYLow 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CursorYHigh 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CursorLocLow 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CursorLocHigh 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CursorXOffset 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CursorYOffset 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CursorFG1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CursorFG2 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CursorFG3 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CursorFG4 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CursorBG1 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CursorBG2 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CursorBG3 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CursorBG4 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CursorControl 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCIRetry 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PreEndControl 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PreEndFetch 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCIMaster 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define Enhancement0 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NewEDO 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TVinterface 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TVMode 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ClockControl 0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* 3CE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MiscExtFunc 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PowerStatus 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MiscIntContReg 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CyberControl 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CyberEnhance 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FPConfig 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VertStretch 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HorStretch 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BiosMode 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BiosReg 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Graphics Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STATUS 0x2120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OLDCMD 0x2124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DRAWFL 0x2128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OLDCLR 0x212C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OLDDST 0x2138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OLDSRC 0x213C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OLDDIM 0x2140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CMD 0x2144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ROP 0x2148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define COLOR 0x2160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BGCOLOR 0x2164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SRC1 0x2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SRC2 0x2104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DST1 0x2108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DST2 0x210C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ROP_S 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ROP_P 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ROP_X 0x66
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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