^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef TGAFB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TGAFB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * TGA hardware description (minimal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TGA_TYPE_8PLANE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TGA_TYPE_24PLANE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TGA_TYPE_24PLUSZ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Offsets within Memory Space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TGA_ROM_OFFSET 0x0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TGA_REGS_OFFSET 0x0100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TGA_8PLANE_FB_OFFSET 0x0200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TGA_24PLANE_FB_OFFSET 0x0804000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TGA_24PLUSZ_FB_OFFSET 0x1004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TGA_FOREGROUND_REG 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TGA_BACKGROUND_REG 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TGA_PLANEMASK_REG 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TGA_PIXELMASK_ONESHOT_REG 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TGA_MODE_REG 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TGA_RASTEROP_REG 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TGA_PIXELSHIFT_REG 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TGA_DEEP_REG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TGA_START_REG 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TGA_PIXELMASK_REG 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TGA_CURSOR_BASE_REG 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TGA_HORIZ_REG 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TGA_VERT_REG 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TGA_BASE_ADDR_REG 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TGA_VALID_REG 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TGA_CURSOR_XY_REG 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TGA_INTR_STAT_REG 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TGA_DATA_REG 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TGA_RAMDAC_SETUP_REG 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TGA_BLOCK_COLOR0_REG 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TGA_BLOCK_COLOR1_REG 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TGA_BLOCK_COLOR2_REG 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TGA_BLOCK_COLOR3_REG 0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TGA_BLOCK_COLOR4_REG 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TGA_BLOCK_COLOR5_REG 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TGA_BLOCK_COLOR6_REG 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TGA_BLOCK_COLOR7_REG 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TGA_COPY64_SRC 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TGA_COPY64_DST 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TGA_CLOCK_REG 0x01e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TGA_RAMDAC_REG 0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TGA_CMD_STAT_REG 0x01f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Useful defines for managing the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TGA_HORIZ_ODD 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TGA_HORIZ_POLARITY 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TGA_HORIZ_ACT_MSB 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TGA_HORIZ_BP 0x0fe00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TGA_HORIZ_SYNC 0x001fc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TGA_HORIZ_FP 0x00007c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TGA_HORIZ_ACT_LSB 0x000001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TGA_VERT_SE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TGA_VERT_POLARITY 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TGA_VERT_RESERVED 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TGA_VERT_BP 0x0fc00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TGA_VERT_SYNC 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TGA_VERT_FP 0x0000f800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TGA_VERT_ACTIVE 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TGA_VALID_VIDEO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TGA_VALID_BLANK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TGA_VALID_CURSOR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TGA_MODE_SBM_8BPP 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TGA_MODE_SBM_24BPP 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TGA_MODE_SIMPLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TGA_MODE_SIMPLEZ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TGA_MODE_OPAQUE_STIPPLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TGA_MODE_OPAQUE_FILL 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TGA_MODE_TRANSPARENT_STIPPLE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TGA_MODE_TRANSPARENT_FILL 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TGA_MODE_BLOCK_STIPPLE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TGA_MODE_BLOCK_FILL 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TGA_MODE_COPY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TGA_MODE_DMA_READ_COPY_ND 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TGA_MODE_DMA_READ_COPY_D 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TGA_MODE_DMA_WRITE_COPY 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Useful defines for managing the ICS1562 PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TGA_PLL_BASE_FREQ 14318 /* .18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TGA_PLL_MAX_FREQ 230000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Useful defines for managing the BT485 on the 8-plane TGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BT485_READ_BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BT485_WRITE_BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BT485_ADDR_PAL_WRITE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BT485_DATA_PAL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BT485_PIXEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BT485_ADDR_PAL_READ 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BT485_ADDR_CUR_WRITE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BT485_DATA_CUR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BT485_CMD_0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BT485_ADDR_CUR_READ 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BT485_CMD_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BT485_CMD_2 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BT485_STATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BT485_CMD_3 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BT485_CUR_RAM 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BT485_CUR_LOW_X 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BT485_CUR_HIGH_X 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BT485_CUR_LOW_Y 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BT485_CUR_HIGH_Y 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BT463_ADDR_LO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BT463_ADDR_HI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BT463_REG_ACC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BT463_PALETTE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BT463_CUR_CLR_0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BT463_CUR_CLR_1 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BT463_CMD_REG_0 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BT463_CMD_REG_1 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BT463_CMD_REG_2 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BT463_READ_MASK_0 0x0205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BT463_READ_MASK_1 0x0206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BT463_READ_MASK_2 0x0207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BT463_READ_MASK_3 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BT463_BLINK_MASK_0 0x0209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BT463_BLINK_MASK_1 0x020a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BT463_BLINK_MASK_2 0x020b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BT463_BLINK_MASK_3 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BT463_WINDOW_TYPE_BASE 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Useful defines for managing the BT459 on the 8-plane SFB+s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BT459_ADDR_LO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BT459_ADDR_HI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BT459_REG_ACC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BT459_PALETTE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BT459_CUR_CLR_1 0x0181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BT459_CUR_CLR_2 0x0182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BT459_CUR_CLR_3 0x0183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BT459_CMD_REG_0 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BT459_CMD_REG_1 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BT459_CMD_REG_2 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BT459_READ_MASK 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BT459_BLINK_MASK 0x0206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BT459_CUR_CMD_REG 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * The framebuffer driver private data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct tga_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* PCI/TC device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Device dependent information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) void __iomem *tga_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void __iomem *tga_fb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *tga_regs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 tga_type; /* TGA_TYPE_XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 tga_chip_rev; /* dc21030 revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Remember blank mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 vesa_blanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Define the video mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 xres, yres; /* resolution in pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 htimings; /* horizontal timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 vtimings; /* vertical timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 pll_freq; /* pixclock in mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 bits_per_pixel; /* bits per pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 sync_on_green; /* set if sync is on green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Macros for reading/writing TGA and RAMDAC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writel(v, par->tga_regs_base +r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) TGA_READ_REG(struct tga_par *par, u32 r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return readl(par->tga_regs_base +r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) BT485_WRITE(struct tga_par *par, u8 v, u8 r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) BT463_LOAD_ADDR(struct tga_par *par, u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) BT463_LOAD_ADDR(par, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) BT459_LOAD_ADDR(struct tga_par *par, u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) BT459_LOAD_ADDR(par, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif /* TGAFB_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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