^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _TDFX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _TDFX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* membase0 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PCIINIT0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SIPMONITOR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LFBMEMORYCONFIG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MISCINIT0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MISCINIT1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DRAMINIT0 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DRAMINIT1 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AGPINIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TMUGBEINIT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VGAINIT0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VGAINIT1 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRAMCOMMAND 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRAMDATA 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* reserved 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* reserved 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLLCTRL0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLLCTRL1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLLCTRL2 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DACMODE 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DACADDR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DACDATA 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RGBMAXDELTA 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VIDPROCCFG 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HWCURPATADDR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HWCURLOC 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HWCURC0 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HWCURC1 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIDINFORMAT 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIDINSTATUS 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VIDSERPARPORT 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VIDINXDELTA 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VIDININITERR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VIDINYDELTA 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VIDPIXBUFTHOLD 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VIDCHRMIN 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VIDCHRMAX 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VIDCURLIN 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VIDSCREENSIZE 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VIDOVRSTARTCRD 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VIDOVRENDCRD 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VIDOVRDUDX 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VIDOVRDUDXOFF 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VIDOVRDVDY 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VIDOVRDVDYOFF 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VIDDESKSTART 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VIDDESKSTRIDE 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VIDINADDR0 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VIDINADDR1 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VIDINADDR2 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VIDINSTRIDE 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VIDCUROVRSTART 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define INTCTRL (0x00100000 + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLIP0MIN (0x00100000 + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLIP0MAX (0x00100000 + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DSTBASE (0x00100000 + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DSTFORMAT (0x00100000 + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SRCBASE (0x00100000 + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define COMMANDEXTRA_2D (0x00100000 + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLIP1MIN (0x00100000 + 0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLIP1MAX (0x00100000 + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SRCFORMAT (0x00100000 + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SRCSIZE (0x00100000 + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SRCXY (0x00100000 + 0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define COLORBACK (0x00100000 + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define COLORFORE (0x00100000 + 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DSTSIZE (0x00100000 + 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DSTXY (0x00100000 + 0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define COMMAND_2D (0x00100000 + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LAUNCH_2D (0x00100000 + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define COMMAND_3D (0x00200000 + 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* register bitfields (not all, only as needed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* COMMAND_2D reg. values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TDFX_ROP_COPY 0xcc /* src */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TDFX_ROP_INVERT 0x55 /* NOT dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TDFX_ROP_XOR 0x66 /* src XOR dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AUTOINC_DSTX BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AUTOINC_DSTY BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define COMMAND_2D_FILLRECT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define COMMAND_2D_S2S_BITBLT 0x01 /* screen to screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define COMMAND_2D_H2S_BITBLT 0x03 /* host to screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define COMMAND_3D_NOP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STATUS_RETRACE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STATUS_BUSY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MISCINIT1_CLUT_INV BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MISCINIT1_2DBLOCK_DIS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRAMINIT0_SGRAM_NUM BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DRAMINIT0_SGRAM_TYPE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRAMINIT0_SGRAM_TYPE_MASK (BIT(27) | BIT(28) | BIT(29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRAMINIT0_SGRAM_TYPE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRAMINIT1_MEM_SDRAM BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VGAINIT0_VGA_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VGAINIT0_EXT_TIMING BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VGAINIT0_8BIT_DAC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VGAINIT0_EXT_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VGAINIT0_WAKEUP_3C3 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VGAINIT0_LEGACY_DISABLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VGAINIT0_ALT_READBACK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VGAINIT0_FAST_BLINK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VGAINIT0_EXTSHIFTOUT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VGAINIT0_DECODE_3C6 BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VGAINIT1_MASK 0x1fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VIDCFG_VIDPROC_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VIDCFG_CURS_X11 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VIDCFG_INTERLACE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VIDCFG_HALF_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VIDCFG_DESK_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIDCFG_CLUT_BYPASS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VIDCFG_2X BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VIDCFG_HWCURSOR_ENABLE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VIDCFG_PIXFMT_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DACMODE_2X BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* I2C bit locations in the VIDSERPARPORT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DDC_ENAB 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DDC_SCL_OUT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DDC_SDA_OUT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DDC_SCL_IN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DDC_SDA_IN 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define I2C_ENAB 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define I2C_SCL_OUT 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define I2C_SDA_OUT 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define I2C_SCL_IN 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define I2C_SDA_IN 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* VGA rubbish, need to change this for multihead support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MISC_W 0x3c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MISC_R 0x3cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SEQ_I 0x3c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SEQ_D 0x3c5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CRT_I 0x3d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CRT_D 0x3d5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ATT_IW 0x3c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IS1_R 0x3da
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GRA_I 0x3ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GRA_D 0x3cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct banshee_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* VGA rubbish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned char att[21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned char crt[25];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned char gra[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned char misc[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned char seq[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Banshee extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned char ext[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long vidcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long vidpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long mempll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long gfxpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long dacmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long vgainit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long vgainit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long screensize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long cursloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long curspataddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long cursc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long cursc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long startaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long clip0min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long clip0max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long clip1min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long clip1max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long miscinit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct tdfx_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct tdfxfb_i2c_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tdfx_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct i2c_algo_bit_data algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct tdfx_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 max_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void __iomem *regbase_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifdef CONFIG_FB_3DFX_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct tdfxfb_i2c_chan chan[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #endif /* _TDFX_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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