^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Created 28 Aug 2001 by Ghozlane Toumi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _SSTFB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _SSTFB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Debug Stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef SST_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define dprintk(X...) printk("sstfb: " X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # define SST_DEBUG_REG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) # define SST_DEBUG_FUNC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define SST_DEBUG_VAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) # define dprintk(X...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # define SST_DEBUG_REG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) # define SST_DEBUG_FUNC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) # define SST_DEBUG_VAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #if (SST_DEBUG_REG > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define r_dprintk(X...) dprintk(X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define r_dprintk(X...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if (SST_DEBUG_REG > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define r_ddprintk(X...) dprintk(" " X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # define r_ddprintk(X...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #if (SST_DEBUG_FUNC > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define f_dprintk(X...) dprintk(X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # define f_dprintk(X...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #if (SST_DEBUG_FUNC > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define f_ddprintk(X...) dprintk(" " X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define f_ddprintk(X...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #if (SST_DEBUG_FUNC > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define f_dddprintk(X...) dprintk(" " X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define f_dddprintk(X...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #if (SST_DEBUG_VAR > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # define v_dprintk(X...) dprintk(X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) # define print_var(V, X...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dprintk(X); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) printk(" :\n"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) sst_dbg_print_var(V); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define v_dprintk(X...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define print_var(X,Y...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define POW2(x) (1ul<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* pci stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_INIT_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define PCI_EN_INIT_WR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) # define PCI_EN_FIFO_WR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define PCI_REMAP_DAC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCI_VCLK_ENABLE 0xc0 /* enable video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCI_VCLK_DISABLE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* register offsets from memBaseAddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define STATUS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define STATUS_FBI_BUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FBZMODE 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define EN_CLIPPING BIT(0) /* enable clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define EN_ALPHA_WRITE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LFBMODE 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define LFB_565 0 /* bits 3:0 .16 bits RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define LFB_888 4 /* 24 bits RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define LFB_8888 5 /* 32 bits ARGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define WR_BUFF_FRONT 0 /* write buf select (front) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) # define WR_BUFF_BACK (1 << 4) /* back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define RD_BUFF_FRONT 0 /* read buff select (front) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define RD_BUFF_BACK (1 << 6) /* back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLIP_LEFT_RIGHT 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLIP_LOWY_HIGHY 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NOPCMD 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FASTFILLCMD 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SWAPBUFFCMD 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FBIINIT4 0x0200 /* misc controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define FAST_PCI_READS 0 /* 1 waitstate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define SLOW_PCI_READS BIT(0) /* 2 ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define LFB_READ_AHEAD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BACKPORCH 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VIDEODIMENSIONS 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FBIINIT0 0x0210 /* misc+fifo controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # define DIS_VGA_PASSTHROUGH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) # define FBI_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define FIFO_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FBIINIT1 0x0214 /* PCI + video controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define FAST_PCI_WRITES 0 /* 0 ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define SLOW_PCI_WRITES BIT(1) /* 1 ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) # define EN_LFB_READ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define TILES_IN_X_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define VIDEO_RESET BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define EN_BLANKING BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define EN_DATA_OE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define EN_BLANK_OE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define EN_HVSYNC_OE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define EN_DCLK_OE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define SEL_INPUT_VCLK_2X 0 /* bit 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define SEL_INPUT_VCLK_SLAVE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define EN_24BPP BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define TILES_IN_X_MSB_SHIFT 24 /* v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) # define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define VCLK_DEL_SHIFT 29 /* vclk in delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FBIINIT2 0x0218 /* Dram controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define EN_FAST_RAS_READ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) # define EN_DRAM_OE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define EN_FAST_RD_AHEAD_WR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) # define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # define SWAP_DACVSYNC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # define SWAP_DACDATA0 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define SWAP_FIFO_STALL (2 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define EN_RD_AHEAD_FIFO BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define EN_DRAM_REFRESH BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) # define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DAC_READ FBIINIT2 /* in remap mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FBIINIT3 0x021c /* fbi controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) # define DISABLE_TEXTURE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap subtraction value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HSYNC 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VSYNC 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DAC_DATA 0x022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define DAC_READ_CMD BIT(11) /* set read dacreg mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FBIINIT5 0x0244 /* v2 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) # define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define HDOUBLESCAN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define VDOUBLESCAN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define HSYNC_HIGH BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) # define VSYNC_HIGH BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) # define INTERLACE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FBIINIT6 0x0248 /* v2 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define TILES_IN_X_LSB_SHIFT 30 /* v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FBIINIT7 0x024c /* v2 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BLTSIZE 0x02e8 /* BitBLT width and height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BLTROP 0x02ec /* BitBLT Raster operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) # define BLTROP_COPY 0x0cccc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define BLTROP_INVERT 0x05555
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define BLTROP_XOR 0x06666
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) # define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) # define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Dac Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DACREG_WMA 0x0 /* pixel write mode address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DACREG_LUT 0x01 /* color value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DACREG_RMR 0x02 /* pixel mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DACREG_RMA 0x03 /* pixel read mode address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*Dac registers in indexed mode (TI, ATT dacs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DACREG_ADDR_I DACREG_WMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DACREG_DATA_I DACREG_RMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DACREG_RMR_I 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DACREG_CR0_I 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) # define DACREG_CR0_16BPP 0x30 /* mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) # define DACREG_CR0_24BPP 0x50 /* mode 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DACREG_CR1_I 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DACREG_CC_I 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) # define DACREG_CC_CLKA BIT(7) /* clk A controlled by regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) # define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) # define DACREG_CC_CLKB BIT(3) /* clk B controlled by regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) # define DACREG_CC_CLKB_D 3 /* clkB uses reg D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DACREG_AC0_I 0x48 /* clock A reg C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DACREG_AC1_I 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DACREG_BD0_I 0x6c /* clock B reg D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DACREG_BD1_I 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* identification constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DACREG_MIR_TI 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DACREG_DIR_TI 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DACREG_MIR_ATT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DACREG_DIR_ATT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* ics dac specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DACREG_ICS_CMD 0x06 /* command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * pll parameter register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * indexed : write addr to PLLWMA, write data in PLLDATA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * for reads use PLLRMA .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * 8 freq registers (0-7) for video clock (CLK0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * 2 freq registers (a-b) for graphic clock (CLK1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DACREG_ICS_PLL_CTRL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) # define DACREG_ICS_CLK0 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) # define DACREG_ICS_CLK0_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) # define DACREG_ICS_CLK1_A 0 /* bit4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* sst default init registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define FBIINIT0_DEFAULT DIS_VGA_PASSTHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define FBIINIT1_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FAST_PCI_WRITES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* SLOW_PCI_WRITES*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) | VIDEO_RESET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) | 10 << TILES_IN_X_SHIFT\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) | SEL_SOURCE_VCLK_2X_SEL\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) | EN_LFB_READ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define FBIINIT2_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SWAP_DACVSYNC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) | EN_DRAM_OE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) | DRAM_REFRESH_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) | EN_DRAM_REFRESH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) | EN_FAST_RAS_READ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) | EN_RD_AHEAD_FIFO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) | EN_FAST_RD_AHEAD_WR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FBIINIT3_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ( DISABLE_TEXTURE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define FBIINIT4_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FAST_PCI_READS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* SLOW_PCI_READS*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) | LFB_READ_AHEAD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Careful with this one : writing back the data just read will trash the DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) reading some fields give logic value on pins, but setting this field will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) set the source signal driving the pin. conclusion : just use the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) as a base before writing back .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define FBIINIT6_DEFAULT (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Misc Const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* ioctl to enable/disable VGA passthrough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SSTFB_SET_VGAPASS _IOW('F', 0xdd, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SSTFB_GET_VGAPASS _IOR('F', 0xdd, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* used to know witch clock to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) VID_CLOCK=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) GFX_CLOCK=1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* freq max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DAC_FREF 14318 /* DAC reference freq (Khz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define VCO_MAX 260000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * driver structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct pll_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct dac_switch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int (*detect) (struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void (*set_vidmod) (struct fb_info *info, const int bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct sst_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) char * name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct sstfb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int yDim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int hSyncOn; /* hsync_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int hSyncOff; /* left_margin + xres + right_margin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int hBackPorch;/* left_margin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int vSyncOn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int vSyncOff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int vBackPorch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct pll_timing pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int tiles_in_X;/* num of tiles in X res */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 __iomem *mmio_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct dac_switch dac_sw; /* dac specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 vgapass; /* VGA pass through: 1=enabled, 0=disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif /* _SSTFB_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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