^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_SH_MOBILE_LCDC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_SH_MOBILE_LCDC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _LDDCKR 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define LDDCKR_ICKSEL_BUS (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define LDDCKR_ICKSEL_MIPI (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LDDCKR_ICKSEL_HDMI (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LDDCKR_ICKSEL_EXT (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LDDCKR_ICKSEL_MASK (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LDDCKR_MOSEL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _LDDCKSTPR 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _LDINTR 0x468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LDINTR_FE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LDINTR_VSE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LDINTR_VEE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LDINTR_FS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LDINTR_VSS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LDINTR_VES (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LDINTR_STATUS_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define _LDSR 0x46c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LDSR_MSS (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LDSR_MRS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LDSR_AS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define _LDCNT1R 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LDCNT1R_DE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define _LDCNT2R 0x474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LDCNT2R_BR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LDCNT2R_MD (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LDCNT2R_SE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LDCNT2R_ME (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LDCNT2R_DO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define _LDRCNTR 0x478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LDRCNTR_SRS (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LDRCNTR_SRC (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LDRCNTR_MRS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LDRCNTR_MRC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define _LDDDSR 0x47c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LDDDSR_LS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LDDDSR_WS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LDDDSR_BS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LDMT1R_VPOL (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LDMT1R_HPOL (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LDMT1R_DWPOL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LDMT1R_DIPOL (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LDMT1R_DAPOL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LDMT1R_HSCNT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LDMT1R_DWCNT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LDMT1R_IFM (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LDMT1R_MIFTYP_RGB18 (0xa << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LDMT1R_MIFTYP_RGB24 (0xb << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LDMT1R_MIFTYP_YCBCR (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LDMT1R_MIFTYP_SYS18 (0xa << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LDMT1R_MIFTYP_SYS24 (0xb << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LDMT1R_MIFTYP_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LDDFR_CF1 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LDDFR_CF0 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LDDFR_CC (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LDDFR_YF_420 (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LDDFR_YF_422 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LDDFR_YF_444 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LDDFR_YF_MASK (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LDDFR_PKF_ARGB32 (0x00 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LDDFR_PKF_RGB16 (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LDDFR_PKF_RGB24 (0x0b << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LDDFR_PKF_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LDSM1R_OS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LDSM2R_OSTRG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LDPMR_LPS (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define _LDDWD0R 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LDDWDxR_WDACT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LDDWDxR_RSW (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define _LDDRDR 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LDDRDR_RSR (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LDDRDR_DRD_MASK (0x3ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define _LDDWAR 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LDDWAR_WA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define _LDDRAR 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LDDRAR_RA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum { LCDC_CHAN_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) LCDC_CHAN_MAINLCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) LCDC_CHAN_SUBLCD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct sh_mobile_lcdc_sys_bus_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long ldmt2r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long ldmt3r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long deferred_io_msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct sh_mobile_lcdc_sys_bus_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void (*write_index)(void *handle, unsigned long data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void (*write_data)(void *handle, unsigned long data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long (*read_data)(void *handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sh_mobile_lcdc_panel_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long width; /* Panel width in mm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long height; /* Panel height in mm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int (*setup_sys)(void *sys_ops_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void (*start_transfer)(void *sys_ops_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void (*display_on)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void (*display_off)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* backlight info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct sh_mobile_lcdc_bl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int max_brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int (*set_brightness)(int brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct sh_mobile_lcdc_overlay_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int max_xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int max_yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct sh_mobile_lcdc_chan_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int interface_type; /* selects RGBn or SYSn I/F, see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int clock_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long flags; /* LCDC_FLAGS_... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const struct fb_videomode *lcd_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct sh_mobile_lcdc_panel_cfg panel_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct sh_mobile_lcdc_bl_info bl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct platform_device *tx_dev; /* HDMI/DSI transmitter device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct sh_mobile_lcdc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int clock_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct sh_mobile_lcdc_chan_cfg ch[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct sh_mobile_lcdc_overlay_cfg overlays[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* __ASM_SH_MOBILE_LCDC_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags