^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* include/video/samsung_fimd.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * S3C Platform - new-style fimd and framebuffer register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This is the register set for the fimd and new style framebuffer interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * found from the S3C2443 onwards into the S3C2416, S3C2450, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * S3C64XX series such as the S3C6400 and S3C6410, and Exynos series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* VIDCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VIDCON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VIDCON0_DSI_EN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VIDCON0_INTERLACE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VIDCON0_VIDOUT_MASK (0x7 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIDCON0_VIDOUT_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VIDCON0_VIDOUT_RGB (0x0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VIDCON0_VIDOUT_TV (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VIDCON0_L1_DATA_MASK (0x7 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VIDCON0_L1_DATA_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VIDCON0_L1_DATA_16BPP (0x0 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VIDCON0_L1_DATA_24BPP (0x3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIDCON0_L1_DATA_18BPP (0x4 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VIDCON0_L0_DATA_MASK (0x7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VIDCON0_L0_DATA_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VIDCON0_L0_DATA_16BPP (0x0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VIDCON0_L0_DATA_24BPP (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VIDCON0_L0_DATA_18BPP (0x4 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VIDCON0_PNRMODE_MASK (0x3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VIDCON0_PNRMODE_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VIDCON0_PNRMODE_RGB (0x0 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VIDCON0_PNRMODE_BGR (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VIDCON0_CLKVALUP (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VIDCON0_CLKVAL_F_MASK (0xff << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VIDCON0_CLKVAL_F_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VIDCON0_CLKVAL_F_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VIDCON0_VLCKFREE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VIDCON0_CLKDIR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VIDCON0_CLKSEL_MASK (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VIDCON0_CLKSEL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VIDCON0_CLKSEL_HCLK (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VIDCON0_CLKSEL_LCD (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VIDCON0_CLKSEL_27M (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VIDCON0_ENVID (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VIDCON0_ENVID_F (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VIDCON1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VIDCON1_LINECNT_MASK (0x7ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VIDCON1_LINECNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VIDCON1_FSTATUS_EVEN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VIDCON1_VSTATUS_MASK (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VIDCON1_VSTATUS_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VIDCON1_VCLK_MASK (0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VIDCON1_VCLK_HOLD (0x0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VIDCON1_VCLK_RUN (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VIDCON1_INV_VCLK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VIDCON1_INV_HSYNC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VIDCON1_INV_VSYNC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VIDCON1_INV_VDEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* VIDCON2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VIDCON2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VIDCON2_EN601 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VIDCON2_TVFMTSEL_SW (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VIDCON2_TVFMTSEL1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VIDCON2_ORGYCbCr (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VIDCON2_YUVORDCrCb (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* PRTCON (S3C6410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Might not be present in the S3C6410 documentation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * but tests prove it's there almost for sure; shouldn't hurt in any case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PRTCON 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PRTCON_PROTECT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* VIDTCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VIDTCON0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VIDTCON0_VBPDE_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VIDTCON0_VBPDE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VIDTCON0_VBPDE_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VIDTCON0_VBPDE(_x) ((_x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VIDTCON0_VBPD_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIDTCON0_VBPD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VIDTCON0_VBPD_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VIDTCON0_VBPD(_x) ((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VIDTCON0_VFPD_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VIDTCON0_VFPD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VIDTCON0_VFPD_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VIDTCON0_VFPD(_x) ((_x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VIDTCON0_VSPW_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VIDTCON0_VSPW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VIDTCON0_VSPW_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VIDTCON0_VSPW(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* VIDTCON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VIDTCON1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VIDTCON1_VFPDE_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VIDTCON1_VFPDE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VIDTCON1_VFPDE_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VIDTCON1_VFPDE(_x) ((_x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VIDTCON1_HBPD_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VIDTCON1_HBPD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VIDTCON1_HBPD_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VIDTCON1_HBPD(_x) ((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VIDTCON1_HFPD_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VIDTCON1_HFPD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VIDTCON1_HFPD_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VIDTCON1_HFPD(_x) ((_x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VIDTCON1_HSPW_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VIDTCON1_HSPW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VIDTCON1_HSPW_LIMIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VIDTCON1_HSPW(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VIDTCON2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VIDTCON2_LINEVAL_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VIDTCON2_LINEVAL_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VIDTCON2_HOZVAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VIDTCON2_HOZVAL_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* WINCONx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define WINCON(_win) (0x20 + ((_win) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define WINCONx_CSCCON_EQ601 (0x0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WINCONx_CSCCON_EQ709 (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define WINCONx_CSCWIDTH_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define WINCONx_ENLOCAL (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define WINCONx_BUFSTATUS (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define WINCONx_BUFSEL (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define WINCONx_BUFAUTOEN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define WINCONx_BITSWP (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define WINCONx_BYTSWP (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define WINCONx_HAWSWP (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define WINCONx_WSWP (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define WINCONx_YCbCr (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define WINCONx_BURSTLEN_MASK (0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define WINCONx_BURSTLEN_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define WINCONx_BURSTLEN_8WORD (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define WINCONx_BURSTLEN_4WORD (0x2 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define WINCONx_ENWIN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define WINCONx_BLEND_MODE_MASK (0xc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define WINCON0_BPPMODE_MASK (0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define WINCON0_BPPMODE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define WINCON0_BPPMODE_1BPP (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define WINCON0_BPPMODE_2BPP (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define WINCON0_BPPMODE_4BPP (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define WINCON1_LOCALSEL_CAMIF (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define WINCON1_ALPHA_MUL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define WINCON1_BLD_PIX (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define WINCON1_BPPMODE_MASK (0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define WINCON1_BPPMODE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define WINCON1_BPPMODE_1BPP (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define WINCON1_BPPMODE_2BPP (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define WINCON1_BPPMODE_4BPP (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define WINCON1_ALPHA_SEL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* S5PV210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SHADOWCON 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* DMA channels (all windows) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Local input channels (windows 0-2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* VIDOSDx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define VIDOSD_BASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define VIDOSDxA_TOPLEFT_X_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define VIDOSDxA_TOPLEFT_X_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VIDOSDxA_TOPLEFT_Y_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VIDOSDxA_TOPLEFT_Y_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define VIDOSDxB_BOTRIGHT_X_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define VIDOSDxB_BOTRIGHT_X_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* For VIDOSD[1..4]C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define VIDISD14C_ALPHA0_G_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define VIDISD14C_ALPHA0_G_LIMIT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define VIDISD14C_ALPHA0_B_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define VIDISD14C_ALPHA0_B_LIMIT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define VIDISD14C_ALPHA1_R_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define VIDISD14C_ALPHA1_R_LIMIT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define VIDISD14C_ALPHA1_G_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define VIDISD14C_ALPHA1_G_LIMIT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define VIDISD14C_ALPHA1_B_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define VIDISD14C_ALPHA1_B_LIMIT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define VIDW_ALPHA 0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define VIDW_ALPHA_R(_x) ((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define VIDW_ALPHA_G(_x) ((_x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define VIDW_ALPHA_B(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Video buffer addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define VIDW_BUF_START_S(_buff) (0x40A0 + ((_buff) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define VIDW_BUF_SIZE_OFFSET_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define VIDW_BUF_SIZE_OFFSET_LIMIT 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Interrupt controls and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define VIDINTCON0 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define VIDINTCON0_FIFOINTERVAL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define VIDINTCON0_FIFOINTERVAL_LIMIT 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define VIDINTCON0_INT_SYSMAINCON (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define VIDINTCON0_INT_SYSSUBCON (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define VIDINTCON0_INT_I80IFDONE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define VIDINTCON0_FRAMESEL0_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define VIDINTCON0_FRAMESEL1 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define VIDINTCON0_INT_FRAME (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define VIDINTCON0_FIFIOSEL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define VIDINTCON0_FIFOLEVEL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define VIDINTCON0_INT_FIFO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define VIDINTCON0_INT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define VIDINTCON1 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define VIDINTCON1_INT_I80 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define VIDINTCON1_INT_FRAME (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define VIDINTCON1_INT_FIFO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Window colour-key control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define WKEYCON 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define WKEYCON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define WKEYCON1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define WxKEYCON0_KEYBL_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define WxKEYCON0_KEYEN_F (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define WxKEYCON0_DIRCON (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define WxKEYCON0_COMPKEY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define WxKEYCON0_COMPKEY_LIMIT 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define WxKEYCON1_COLVAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define WxKEYCON1_COLVAL_LIMIT 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define WxKEYCON1_COLVAL(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Dithering control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define DITHMODE 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define DITHMODE_R_POS_MASK (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DITHMODE_R_POS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DITHMODE_R_POS_8BIT (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DITHMODE_R_POS_6BIT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DITHMODE_R_POS_5BIT (0x2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DITHMODE_G_POS_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DITHMODE_G_POS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define DITHMODE_G_POS_8BIT (0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DITHMODE_G_POS_6BIT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DITHMODE_G_POS_5BIT (0x2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DITHMODE_B_POS_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DITHMODE_B_POS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DITHMODE_B_POS_8BIT (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DITHMODE_B_POS_6BIT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DITHMODE_B_POS_5BIT (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DITHMODE_DITH_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Window blanking (MAP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define WINxMAP(_win) (0x180 + ((_win) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define WINxMAP_MAP (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define WINxMAP_MAP_COLOUR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Winodw palette control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define WPALCON 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define WPALCON_PAL_UPDATE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define WPALCON_W4PAL_16BPP_A555 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define WPALCON_W3PAL_16BPP_A555 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define WPALCON_W2PAL_16BPP_A555 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define WPALCON_W1PAL_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define WPALCON_W1PAL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define WPALCON_W1PAL_24BPP (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define WPALCON_W1PAL_18BPP (0x4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define WPALCON_W0PAL_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define WPALCON_W0PAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define WPALCON_W0PAL_24BPP (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define WPALCON_W0PAL_18BPP (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Blending equation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define BLENDEQx(_win) (0x244 + ((_win - 1) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define BLENDEQ_ZERO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define BLENDEQ_ONE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define BLENDEQ_ALPHA_A 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define BLENDEQ_ONE_MINUS_ALPHA_A 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define BLENDEQ_ALPHA0 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define BLENDEQ_B_FUNC_F(_x) (_x << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define BLENDEQ_A_FUNC_F(_x) (_x << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define BLENDCON 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define BLENDCON_NEW_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Display port clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define DP_MIE_CLKCON 0x27c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define DP_MIE_CLK_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DP_MIE_CLK_DP_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define DP_MIE_CLK_MIE_ENABLE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Notes on per-window bpp settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Value Win0 Win1 Win2 Win3 Win 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * 0010 4(P) 4(P) 4(P) 4(P) -none-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * 0011 8(P) 8(P) -none- -none- -none-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * 0100 -none- 8(A232) 8(A232) -none- -none-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * 1110 -none- -none- -none- -none- -none-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * 1111 -none- -none- -none- -none- -none-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* FIMD Version 8 register offset definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define FIMD_V8_VIDTCON0 0x20010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define FIMD_V8_VIDTCON1 0x20014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define FIMD_V8_VIDTCON2 0x20018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FIMD_V8_VIDTCON3 0x2001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define FIMD_V8_VIDCON1 0x20004
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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