^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* include/video/s1d13xxxfb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (c) 2004 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Header file for Epson S1D13XXX driver code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef S1D13XXXFB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S1D13XXXFB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S1D_PALETTE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S1D_FBID "S1D13xxx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S1D_DEVICENAME "s1d13xxxfb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S1D13505_PROD_ID 0x3 /* 000011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S1D13506_PROD_ID 0x4 /* 000100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S1D13806_PROD_ID 0x7 /* 000111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* register definitions (tested on s1d13896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S1DREG_DELAYOFF 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S1DREG_DELAYON 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BBLT_SOLID_FILL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Note: all above defines should go in separate header files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) when implementing other S1D13xxx chip support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct s1d13xxxfb_regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct s1d13xxxfb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned char display;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned char prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned char revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void *regs_save; /* pm saves all registers here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void *disp_save; /* pm saves entire screen here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct s1d13xxxfb_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const struct s1d13xxxfb_regval *initregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const unsigned int initregssize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void (*platform_init_video)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int (*platform_suspend_video)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int (*platform_resume_video)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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