^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _RADEON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _RADEON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define RADEON_REGSIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MM_INDEX 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MM_DATA 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BUS_CNTL 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HI_STAT 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BUS_CNTL1 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define I2C_CNTL_1 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CNFG_CNTL 0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CNFG_MEMSIZE 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CNFG_APER_0_BASE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CNFG_APER_1_BASE 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CNFG_APER_SIZE 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CNFG_REG_1_BASE 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CNFG_REG_APER_SIZE 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PAD_AGPINPUT_DELAY 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PAD_CTLR_STRENGTH 0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PAD_CTLR_UPDATE 0x016C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PAD_CTLR_MISC 0x0aa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AGP_CNTL 0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BM_STATUS 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CAP0_TRIG_CNTL 0x0950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CAP1_TRIG_CNTL 0x09c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VIPH_CONTROL 0x0C40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VENDOR_ID 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DEVICE_ID 0x0F02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define COMMAND 0x0F04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STATUS 0x0F06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REVISION_ID 0x0F08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REGPROG_INF 0x0F09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUB_CLASS 0x0F0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BASE_CODE 0x0F0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CACHE_LINE 0x0F0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LATENCY 0x0F0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HEADER 0x0F0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BIST 0x0F0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_MEM_BASE 0x0F10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_IO_BASE 0x0F14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_REG_BASE 0x0F18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADAPTER_ID 0x0F2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BIOS_ROM 0x0F30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CAPABILITIES_PTR 0x0F34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define INTERRUPT_LINE 0x0F3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define INTERRUPT_PIN 0x0F3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MIN_GRANT 0x0F3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX_LATENCY 0x0F3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADAPTER_ID_W 0x0F4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PMI_CAP_ID 0x0F50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PMI_NXT_CAP_PTR 0x0F51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PMI_PMC_REG 0x0F52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PM_STATUS 0x0F54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PMI_DATA 0x0F57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AGP_CAP_ID 0x0F58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AGP_STATUS 0x0F5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AGP_COMMAND 0x0F60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AIC_CTRL 0x01D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AIC_STAT 0x01D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AIC_PT_BASE 0x01D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AIC_LO_ADDR 0x01DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AIC_HI_ADDR 0x01E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AIC_TLB_ADDR 0x01E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AIC_TLB_DATA 0x01E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DAC_CNTL 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DAC_CNTL2 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CRTC_GEN_CNTL 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MEM_CNTL 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MC_CNTL 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EXT_MEM_CNTL 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MC_TIMING_CNTL 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MC_AGP_LOCATION 0x014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MEM_IO_CNTL_A0 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MEM_REFRESH_CNTL 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MEM_INIT_LATENCY_TIMER 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MC_INIT_GFX_LAT_TIMER 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MEM_SDRAM_MODE_REG 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AGP_BASE 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MEM_IO_CNTL_A1 0x017C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MC_READ_CNTL_AB 0x017C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MEM_IO_CNTL_B0 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MC_INIT_MISC_LAT_TIMER 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MEM_IO_CNTL_B1 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MC_IOPAD_CNTL 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MC_DEBUG 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MC_STATUS 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MEM_IO_OE_CNTL 0x018C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MC_CHIP_IO_OE_CNTL_AB 0x018C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MC_FB_LOCATION 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HOST_PATH_CNTL 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MEM_VGA_WP_SEL 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MEM_VGA_RP_SEL 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HDP_DEBUG 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SW_SEMAPHORE 0x013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CRTC2_GEN_CNTL 0x03f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CRTC2_DISPLAY_BASE_ADDR 0x033c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SURFACE_CNTL 0x0B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SURFACE0_LOWER_BOUND 0x0B04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SURFACE1_LOWER_BOUND 0x0B14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SURFACE2_LOWER_BOUND 0x0B24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SURFACE3_LOWER_BOUND 0x0B34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SURFACE4_LOWER_BOUND 0x0B44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SURFACE5_LOWER_BOUND 0x0B54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SURFACE6_LOWER_BOUND 0x0B64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SURFACE7_LOWER_BOUND 0x0B74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SURFACE0_UPPER_BOUND 0x0B08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SURFACE1_UPPER_BOUND 0x0B18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SURFACE2_UPPER_BOUND 0x0B28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SURFACE3_UPPER_BOUND 0x0B38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SURFACE4_UPPER_BOUND 0x0B48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SURFACE5_UPPER_BOUND 0x0B58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SURFACE6_UPPER_BOUND 0x0B68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SURFACE7_UPPER_BOUND 0x0B78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SURFACE0_INFO 0x0B0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SURFACE1_INFO 0x0B1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SURFACE2_INFO 0x0B2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SURFACE3_INFO 0x0B3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SURFACE4_INFO 0x0B4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SURFACE5_INFO 0x0B5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SURFACE6_INFO 0x0B6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SURFACE7_INFO 0x0B7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SURFACE_ACCESS_FLAGS 0x0BF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SURFACE_ACCESS_CLR 0x0BFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GEN_INT_CNTL 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GEN_INT_STATUS 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CRTC_EXT_CNTL 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RB3D_CNTL 0x1C3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WAIT_UNTIL 0x1720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ISYNC_CNTL 0x1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RBBM_GUICNTL 0x172C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RBBM_STATUS 0x0E40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RBBM_STATUS_alt_1 0x1740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RBBM_CNTL 0x00EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RBBM_CNTL_alt_1 0x0E44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RBBM_SOFT_RESET 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RBBM_SOFT_RESET_alt_1 0x0E48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NQWAIT_UNTIL 0x0E50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RBBM_DEBUG 0x0E6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RBBM_CMDFIFO_ADDR 0x0E70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RBBM_CMDFIFO_DATAL 0x0E74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RBBM_CMDFIFO_DATAH 0x0E78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RBBM_CMDFIFO_STAT 0x0E7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CRTC_STATUS 0x005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPIO_VGA_DDC 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPIO_DVI_DDC 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GPIO_MONID 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GPIO_CRT2_DDC 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PALETTE_INDEX 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PALETTE_DATA 0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PALETTE_30_DATA 0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CRTC_H_TOTAL_DISP 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CRTC_H_SYNC_STRT_WID 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CRTC_V_TOTAL_DISP 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CRTC_V_SYNC_STRT_WID 0x020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CRTC_VLINE_CRNT_VLINE 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CRTC_CRNT_FRAME 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CRTC_GUI_TRIG_VLINE 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CRTC_DEBUG 0x021C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CRTC_OFFSET_RIGHT 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CRTC_OFFSET 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CRTC_OFFSET_CNTL 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CRTC_PITCH 0x022C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OVR_CLR 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OVR_WID_LEFT_RIGHT 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OVR_WID_TOP_BOTTOM 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DISPLAY_BASE_ADDR 0x023C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SNAPSHOT_VH_COUNTS 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SNAPSHOT_F_COUNT 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define N_VIF_COUNT 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SNAPSHOT_VIF_COUNT 0x024C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FP_CRTC_H_TOTAL_DISP 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FP_CRTC_V_TOTAL_DISP 0x0254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CRT_CRTC_H_SYNC_STRT_WID 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CRT_CRTC_V_SYNC_STRT_WID 0x025C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CUR_OFFSET 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CUR_HORZ_VERT_POSN 0x0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CUR_HORZ_VERT_OFF 0x0268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CUR_CLR0 0x026C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CUR_CLR1 0x0270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FP_HORZ_VERT_ACTIVE 0x0278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CRTC_MORE_CNTL 0x027C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DAC_EXT_CNTL 0x0280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FP_GEN_CNTL 0x0284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FP_HORZ_STRETCH 0x028C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FP_VERT_STRETCH 0x0290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FP_H_SYNC_STRT_WID 0x02C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FP_V_SYNC_STRT_WID 0x02C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AUX_WINDOW_HORZ_CNTL 0x02D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AUX_WINDOW_VERT_CNTL 0x02DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) //#define DDA_CONFIG 0x02e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) //#define DDA_ON_OFF 0x02e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DVI_I2C_CNTL_1 0x02e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GRPH_BUFFER_CNTL 0x02F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GRPH2_BUFFER_CNTL 0x03F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VGA_BUFFER_CNTL 0x02F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OV0_Y_X_START 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OV0_Y_X_END 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OV0_PIPELINE_CNTL 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OV0_REG_LOAD_CNTL 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OV0_SCALE_CNTL 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OV0_V_INC 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OV0_P1_V_ACCUM_INIT 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OV0_P23_V_ACCUM_INIT 0x042C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OV0_P1_BLANK_LINES_AT_TOP 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OV0_P23_BLANK_LINES_AT_TOP 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OV0_BASE_ADDR 0x043C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OV0_VID_BUF0_BASE_ADRS 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OV0_VID_BUF1_BASE_ADRS 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OV0_VID_BUF2_BASE_ADRS 0x0448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OV0_VID_BUF3_BASE_ADRS 0x044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OV0_VID_BUF4_BASE_ADRS 0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OV0_VID_BUF5_BASE_ADRS 0x0454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OV0_VID_BUF_PITCH0_VALUE 0x0460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OV0_VID_BUF_PITCH1_VALUE 0x0464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OV0_AUTO_FLIP_CNTRL 0x0470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OV0_DEINTERLACE_PATTERN 0x0474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OV0_SUBMIT_HISTORY 0x0478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OV0_H_INC 0x0480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OV0_STEP_BY 0x0484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OV0_P1_H_ACCUM_INIT 0x0488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OV0_P23_H_ACCUM_INIT 0x048C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OV0_P1_X_START_END 0x0494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OV0_P2_X_START_END 0x0498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OV0_P3_X_START_END 0x049C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OV0_FILTER_CNTL 0x04A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OV0_FOUR_TAP_COEF_0 0x04B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OV0_FOUR_TAP_COEF_1 0x04B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OV0_FOUR_TAP_COEF_2 0x04B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OV0_FOUR_TAP_COEF_3 0x04BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OV0_FOUR_TAP_COEF_4 0x04C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OV0_FLAG_CNTRL 0x04DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OV0_SLICE_CNTL 0x04E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define OV0_VID_KEY_CLR_LOW 0x04E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OV0_VID_KEY_CLR_HIGH 0x04E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OV0_GRPH_KEY_CLR_LOW 0x04EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OV0_GRPH_KEY_CLR_HIGH 0x04F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OV0_KEY_CNTL 0x04F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OV0_TEST 0x04F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SUBPIC_CNTL 0x0540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SUBPIC_DEFCOLCON 0x0544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SUBPIC_Y_X_START 0x054C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SUBPIC_Y_X_END 0x0550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SUBPIC_V_INC 0x0554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SUBPIC_H_INC 0x0558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SUBPIC_BUF0_OFFSET 0x055C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SUBPIC_BUF1_OFFSET 0x0560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SUBPIC_LC0_OFFSET 0x0564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SUBPIC_LC1_OFFSET 0x0568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SUBPIC_PITCH 0x056C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SUBPIC_BTN_HLI_COLCON 0x0570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SUBPIC_BTN_HLI_Y_X_START 0x0574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SUBPIC_BTN_HLI_Y_X_END 0x0578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SUBPIC_PALETTE_INDEX 0x057C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SUBPIC_PALETTE_DATA 0x0580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SUBPIC_H_ACCUM_INIT 0x0584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SUBPIC_V_ACCUM_INIT 0x0588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DISP_MISC_CNTL 0x0D00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DAC_MACRO_CNTL 0x0D04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DISP_PWR_MAN 0x0D08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DISP_TEST_DEBUG_CNTL 0x0D10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DISP_HW_DEBUG 0x0D14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DAC_CRC_SIG1 0x0D18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DAC_CRC_SIG2 0x0D1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OV0_LIN_TRANS_A 0x0D20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OV0_LIN_TRANS_B 0x0D24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OV0_LIN_TRANS_C 0x0D28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OV0_LIN_TRANS_D 0x0D2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OV0_LIN_TRANS_E 0x0D30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OV0_LIN_TRANS_F 0x0D34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OV0_GAMMA_0_F 0x0D40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OV0_GAMMA_10_1F 0x0D44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define OV0_GAMMA_20_3F 0x0D48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OV0_GAMMA_40_7F 0x0D4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OV0_GAMMA_380_3BF 0x0D50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OV0_GAMMA_3C0_3FF 0x0D54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DISP_MERGE_CNTL 0x0D60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DISP_OUTPUT_CNTL 0x0D64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DISP_LIN_TRANS_GRPH_A 0x0D80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DISP_LIN_TRANS_GRPH_B 0x0D84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DISP_LIN_TRANS_GRPH_C 0x0D88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DISP_LIN_TRANS_GRPH_D 0x0D8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DISP_LIN_TRANS_GRPH_E 0x0D90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DISP_LIN_TRANS_GRPH_F 0x0D94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DISP_LIN_TRANS_VID_A 0x0D98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DISP_LIN_TRANS_VID_B 0x0D9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DISP_LIN_TRANS_VID_C 0x0DA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DISP_LIN_TRANS_VID_D 0x0DA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DISP_LIN_TRANS_VID_E 0x0DA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DISP_LIN_TRANS_VID_F 0x0DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define RMX_HORZ_PHASE 0x0DBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DAC_BROAD_PULSE 0x0DC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DAC_SKEW_CLKS 0x0DC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DAC_INCR 0x0DCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DAC_NEG_SYNC_LEVEL 0x0DD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DAC_POS_SYNC_LEVEL 0x0DD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DAC_BLANK_LEVEL 0x0DD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLOCK_CNTL_INDEX 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLOCK_CNTL_DATA 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CP_RB_CNTL 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CP_RB_BASE 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CP_RB_RPTR_ADDR 0x070C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CP_RB_RPTR 0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CP_RB_WPTR 0x0714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CP_RB_WPTR_DELAY 0x0718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CP_IB_BASE 0x0738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CP_IB_BUFSZ 0x073C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SCRATCH_REG0 0x15E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GUI_SCRATCH_REG0 0x15E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SCRATCH_REG1 0x15E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GUI_SCRATCH_REG1 0x15E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SCRATCH_REG2 0x15E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GUI_SCRATCH_REG2 0x15E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SCRATCH_REG3 0x15EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define GUI_SCRATCH_REG3 0x15EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SCRATCH_REG4 0x15F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define GUI_SCRATCH_REG4 0x15F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SCRATCH_REG5 0x15F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define GUI_SCRATCH_REG5 0x15F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SCRATCH_UMSK 0x0770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SCRATCH_ADDR 0x0774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DP_BRUSH_FRGD_CLR 0x147C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DP_BRUSH_BKGD_CLR 0x1478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DST_LINE_START 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DST_LINE_END 0x1604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SRC_OFFSET 0x15AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SRC_PITCH 0x15B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SRC_TILE 0x1704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SRC_PITCH_OFFSET 0x1428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SRC_X 0x1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRC_Y 0x1418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRC_X_Y 0x1590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRC_Y_X 0x1434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DST_Y_X 0x1438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DST_WIDTH_HEIGHT 0x1598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DST_HEIGHT_WIDTH 0x143c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DST_OFFSET 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SRC_CLUT_ADDRESS 0x1780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRC_CLUT_DATA 0x1784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRC_CLUT_DATA_RD 0x1788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define HOST_DATA0 0x17C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define HOST_DATA1 0x17C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define HOST_DATA2 0x17C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define HOST_DATA3 0x17CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define HOST_DATA4 0x17D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define HOST_DATA5 0x17D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define HOST_DATA6 0x17D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define HOST_DATA7 0x17DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define HOST_DATA_LAST 0x17E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DP_SRC_ENDIAN 0x15D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DP_SRC_FRGD_CLR 0x15D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DP_SRC_BKGD_CLR 0x15DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SC_LEFT 0x1640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SC_RIGHT 0x1644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SC_TOP 0x1648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SC_BOTTOM 0x164C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRC_SC_RIGHT 0x1654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRC_SC_BOTTOM 0x165C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DP_CNTL 0x16C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DP_DATATYPE 0x16C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DP_MIX 0x16C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DP_WRITE_MSK 0x16CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DP_XOP 0x17F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CLR_CMP_CLR_SRC 0x15C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLR_CMP_CLR_DST 0x15C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CLR_CMP_CNTL 0x15C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CLR_CMP_MSK 0x15CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DSTCACHE_MODE 0x1710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DSTCACHE_CTLSTAT 0x1714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DEFAULT_PITCH_OFFSET 0x16E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DEFAULT_SC_TOP_LEFT 0x16EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SRC_PITCH_OFFSET 0x1428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define DST_PITCH_OFFSET 0x142C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define DP_GUI_MASTER_CNTL 0x146C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SC_TOP_LEFT 0x16EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SC_BOTTOM_RIGHT 0x16F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SRC_SC_BOTTOM_RIGHT 0x16F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define RB2D_DSTCACHE_MODE 0x3428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define LVDS_GEN_CNTL 0x02d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define LVDS_PLL_CNTL 0x02d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define FP2_GEN_CNTL 0x0288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define TMDS_CNTL 0x0294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TMDS_CRC 0x02a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TMDS_TRANSMITTER_CNTL 0x02a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MPP_TB_CONFIG 0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PAMAC0_DLY_CNTL 0x0a94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PAMAC1_DLY_CNTL 0x0a98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PAMAC2_DLY_CNTL 0x0a9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define FW_CNTL 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define FCP_CNTL 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define VGA_DDA_ON_OFF 0x02ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TV_MASTER_CNTL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) //#define BASE_CODE 0x0f0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define BIOS_0_SCRATCH 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define BIOS_1_SCRATCH 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define BIOS_2_SCRATCH 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define BIOS_3_SCRATCH 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define BIOS_4_SCRATCH 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define BIOS_5_SCRATCH 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define BIOS_6_SCRATCH 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define BIOS_7_SCRATCH 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define HDP_SOFT_RESET (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define TV_DAC_CNTL 0x088c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define GPIOPAD_MASK 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define GPIOPAD_A 0x019c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define GPIOPAD_EN 0x01a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define GPIOPAD_Y 0x01a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define ZV_LCDPAD_MASK 0x01a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define ZV_LCDPAD_A 0x01ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define ZV_LCDPAD_EN 0x01b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define ZV_LCDPAD_Y 0x01b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* PLL Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CLK_PIN_CNTL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PPLL_CNTL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PPLL_REF_DIV 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PPLL_DIV_0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PPLL_DIV_1 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PPLL_DIV_2 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PPLL_DIV_3 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define VCLK_ECP_CNTL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define HTOTAL_CNTL 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define M_SPLL_REF_FB_DIV 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define AGP_PLL_CNTL 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SPLL_CNTL 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SCLK_CNTL 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MPLL_CNTL 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MDLL_CKO 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MDLL_RDCKA 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MCLK_CNTL 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define AGP_PLL_CNTL 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PLL_TEST_CNTL 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define CLK_PWRMGT_CNTL 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PLL_PWRMGT_CNTL 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MCLK_MISC 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define P2PLL_CNTL 0x002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define P2PLL_REF_DIV 0x002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PIXCLKS_CNTL 0x002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SCLK_MORE_CNTL 0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* MCLK_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define FORCEON_MCLKA (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define FORCEON_MCLKB (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define FORCEON_YCLKA (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define FORCEON_YCLKB (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define FORCEON_MC (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define FORCEON_AIC (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* SCLK_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DYN_STOP_LAT_MASK 0x00007ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CP_MAX_DYN_STOP_LAT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SCLK_FORCEON_MASK 0xffff8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* SCLK_MORE_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SCLK_MORE_FORCEON 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* BUS_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define BUS_DBL_RESYNC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define BUS_MSTR_RESET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define BUS_FLUSH_BUF 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define BUS_STOP_REQ_DIS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define BUS_ROTATION_DIS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define BUS_MASTER_DIS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define BUS_ROM_WRT_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define BUS_DIS_ROM 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define BUS_PCI_READ_RETRY_EN 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define BUS_AGP_AD_STEPPING_EN 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define BUS_PCI_WRT_RETRY_EN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define BUS_MSTR_RD_MULT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define BUS_MSTR_RD_LINE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define BUS_SUSPEND 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define LAT_16X 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define BUS_RD_DISCARD_EN 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define BUS_RD_ABORT_EN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define BUS_MSTR_WS 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define BUS_PARKING_DIS 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define BUS_MSTR_DISCONNECT_EN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define BUS_WRT_BURST 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define BUS_READ_BURST 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define BUS_RDY_READ_DLY 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* PIXCLKS_CNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define PIX2CLK_SRC_SEL_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define PIX2CLK_SRC_SEL_CPUCLK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define PIX2CLK_SRC_SEL_PSCANCLK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define PIX2CLK_SRC_SEL_BYTECLK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PIX2CLK_ALWAYS_ONb (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define PIX2CLK_DAC_ALWAYS_ONb (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define PIXCLK_TV_SRC_SEL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* CLOCK_CNTL_INDEX bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define PLL_WR_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* CNFG_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define CFG_VGA_RAM_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define CFG_ATI_REV_ID_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define CFG_ATI_REV_A11 (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define CFG_ATI_REV_A12 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define CFG_ATI_REV_A13 (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* CRTC_EXT_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define VGA_ATI_LINEAR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define VGA_128KAP_PAGING 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define XCRT_CNT_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define CRTC_HSYNC_DIS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define CRTC_VSYNC_DIS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define CRTC_DISPLAY_DIS (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define CRTC_CRT_ON (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* DSTCACHE_CTLSTAT bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define RB2D_DC_FLUSH_2D (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define RB2D_DC_FREE_2D (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define RB2D_DC_BUSY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* DSTCACHE_MODE bits constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* CRTC_GEN_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define CRTC_DBL_SCAN_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define CRTC_CUR_EN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define CRTC_INTERLACE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define CRTC_BYPASS_LUT_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define CRTC_EXT_DISP_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define CRTC_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define CRTC_DISP_REQ_EN_B (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* CRTC_STATUS bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define CRTC_VBLANK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* CRTC2_GEN_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define CRT2_ON (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define CRTC2_DISPLAY_DIS (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define CRTC2_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define CRTC2_DISP_REQ_EN_B (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define CUR_LOCK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* GPIO bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define GPIO_A_0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define GPIO_A_1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define GPIO_Y_0 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define GPIO_Y_1 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define GPIO_EN_0 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define GPIO_EN_1 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define GPIO_MASK_0 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define GPIO_MASK_1 (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define VGA_DDC_DATA_OUTPUT GPIO_A_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define VGA_DDC_CLK_OUTPUT GPIO_A_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define VGA_DDC_DATA_INPUT GPIO_Y_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define VGA_DDC_CLK_INPUT GPIO_Y_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define VGA_DDC_DATA_OUT_EN GPIO_EN_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define VGA_DDC_CLK_OUT_EN GPIO_EN_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* FP bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define FP_CRTC_H_TOTAL_MASK 0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define FP_CRTC_H_DISP_MASK 0x01ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define FP_CRTC_V_TOTAL_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define FP_CRTC_V_DISP_MASK 0x0fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define FP_H_SYNC_WID_MASK 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define FP_V_SYNC_STRT_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define FP_V_SYNC_WID_MASK 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define FP_CRTC_H_TOTAL_SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define FP_CRTC_H_DISP_SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define FP_CRTC_V_TOTAL_SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define FP_CRTC_V_DISP_SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define FP_H_SYNC_WID_SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define FP_V_SYNC_STRT_SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define FP_V_SYNC_WID_SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* FP_GEN_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define FP_FPON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define FP_TMDS_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define FP_PANEL_FORMAT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define FP_EN_TMDS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define FP_DETECT_SENSE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define R200_FP_SOURCE_SEL_MASK (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define R200_FP_SOURCE_SEL_RMX (2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define R200_FP_SOURCE_SEL_TRANS (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define FP_SEL_CRTC1 (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define FP_SEL_CRTC2 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define FP_USE_VGA_HSYNC (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define FP_CRTC_USE_SHADOW_VEND (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define FP_DFP_SYNC_SEL (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define FP_CRTC_LOCK_8DOT (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define FP_CRT_SYNC_SEL (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define FP_USE_SHADOW_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define FP_CRT_SYNC_ALT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* FP2_GEN_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define FP2_BLANK_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define FP2_ON (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define FP2_PANEL_FORMAT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define FP2_SOURCE_SEL_MASK (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define FP2_SOURCE_SEL_CRTC2 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define FP2_SRC_SEL_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define FP2_SRC_SEL_CRTC2 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define FP2_FP_POL (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define FP2_LP_POL (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define FP2_SCK_POL (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define FP2_LCD_CNTL_MASK (7 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define FP2_PAD_FLOP_EN (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define FP2_CRC_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define FP2_CRC_READ_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define FP2_DV0_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define FP2_DV0_RATE_SEL_SDR (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* LVDS_GEN_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define LVDS_ON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define LVDS_DISPLAY_DIS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define LVDS_PANEL_TYPE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define LVDS_PANEL_FORMAT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define LVDS_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define LVDS_BL_MOD_LEVEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define LVDS_BL_MOD_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define LVDS_DIGON (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define LVDS_BLON (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define LVDS_SEL_CRTC2 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define LVDS_STATE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* LVDS_PLL_CNTL bit constatns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define HSYNC_DELAY_SHIFT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define HSYNC_DELAY_MASK (0xf << 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* TMDS_TRANSMITTER_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define TMDS_PLL_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define TMDS_PLLRST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define TMDS_RAN_PAT_RST (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define TMDS_ICHCSEL (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* FP_HORZ_STRETCH bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define HORZ_STRETCH_RATIO_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define HORZ_STRETCH_RATIO_MAX 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define HORZ_PANEL_SIZE (0x1ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define HORZ_PANEL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define HORZ_STRETCH_PIXREP (0 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define HORZ_STRETCH_BLEND (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define HORZ_STRETCH_ENABLE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define HORZ_AUTO_RATIO (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define HORZ_FP_LOOP_STRETCH (0x7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define HORZ_AUTO_RATIO_INC (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* FP_VERT_STRETCH bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define VERT_STRETCH_RATIO_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define VERT_STRETCH_RATIO_MAX 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define VERT_PANEL_SIZE (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define VERT_PANEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define VERT_STRETCH_LINREP (0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define VERT_STRETCH_BLEND (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define VERT_STRETCH_ENABLE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define VERT_AUTO_RATIO_EN (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define VERT_FP_LOOP_STRETCH (0x7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define VERT_STRETCH_RESERVED 0xf1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* DAC_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define DAC_8BIT_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define DAC_4BPP_PIX_ORDER 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define DAC_CRC_EN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define DAC_MASK_ALL (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define DAC_PDWN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define DAC_EXPAND_MODE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define DAC_VGA_ADR_EN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define DAC_RANGE_CNTL (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define DAC_RANGE_CNTL_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define DAC_BLANKING (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define DAC_CMP_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define DAC_CMP_OUTPUT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* DAC_CNTL2 bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define DAC2_EXPAND_MODE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define DAC2_CMP_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* DAC_EXT_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define DAC_FORCE_BLANK_OFF_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define DAC_FORCE_DATA_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define DAC_FORCE_DATA_SEL_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define DAC_FORCE_DATA_MASK 0x0003ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define DAC_FORCE_DATA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* GEN_RESET_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define SOFT_RESET_GUI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define SOFT_RESET_VCLK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define SOFT_RESET_PCLK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define SOFT_RESET_ECP 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define SOFT_RESET_DISPENG_XCLK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* MEM_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define MEM_CTLR_STATUS_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define MEM_CTLR_STATUS_BUSY 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define MEM_SEQNCR_STATUS_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define MEM_SEQNCR_STATUS_BUSY 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define MEM_ARBITER_STATUS_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define MEM_ARBITER_STATUS_BUSY 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define MEM_REQ_UNLOCK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define MEM_REQ_LOCK 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define MEM_NUM_CHANNELS_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define MEM_USE_B_CH_ONLY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define RV100_MEM_HALF_MODE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define R300_MEM_NUM_CHANNELS_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define R300_MEM_USE_CD_CH_ONLY 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* RBBM_SOFT_RESET bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SOFT_RESET_CP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SOFT_RESET_HI (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SOFT_RESET_SE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define SOFT_RESET_RE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define SOFT_RESET_PP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SOFT_RESET_E2 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define SOFT_RESET_RB (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define SOFT_RESET_HDP (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* WAIT_UNTIL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define WAIT_DMA_GUI_IDLE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define WAIT_2D_IDLECLEAN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* SURFACE_CNTL bit consants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SURF_TRANSLATION_DIS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define NONSURF_AP0_SWP_16BPP (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define NONSURF_AP0_SWP_32BPP (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define NONSURF_AP1_SWP_16BPP (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define NONSURF_AP1_SWP_32BPP (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* MM_INDEX bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define MM_APER 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* CLR_CMP_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define COMPARE_SRC_FALSE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define COMPARE_SRC_TRUE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define COMPARE_SRC_NOT_EQUAL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define COMPARE_SRC_EQUAL 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define COMPARE_SRC_EQUAL_FLIP 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define COMPARE_DST_FALSE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define COMPARE_DST_TRUE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define COMPARE_DST_NOT_EQUAL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define COMPARE_DST_EQUAL 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define COMPARE_DESTINATION 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define COMPARE_SOURCE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define COMPARE_SRC_AND_DST 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* DP_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define DST_X_RIGHT_TO_LEFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define DST_X_LEFT_TO_RIGHT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define DST_Y_BOTTOM_TO_TOP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define DST_Y_TOP_TO_BOTTOM 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define DST_X_MAJOR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define DST_Y_MAJOR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define DST_X_TILE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define DST_Y_TILE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define DST_LAST_PEL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define DST_BRES_SIGN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define DST_HOST_BIG_ENDIAN_EN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define DST_POLYLINE_NONLAST 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define DST_RASTER_STALL 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define DST_POLY_EDGE 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define DST_X_MAJOR_S 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define DST_Y_MAJOR_S 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define DST_Y_BOTTOM_TO_TOP_S 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define DST_Y_TOP_TO_BOTTOM_S 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define DST_X_RIGHT_TO_LEFT_S 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define DST_X_LEFT_TO_RIGHT_S 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* DP_DATATYPE bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define DST_8BPP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define DST_15BPP 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define DST_16BPP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define DST_24BPP 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define DST_32BPP 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define DST_8BPP_RGB332 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define DST_8BPP_Y8 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define DST_8BPP_RGB8 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define DST_16BPP_VYUY422 0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define DST_16BPP_YVYU422 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define DST_32BPP_AYUV444 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define DST_16BPP_ARGB4444 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define BRUSH_SOLIDCOLOR 0x00000d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define SRC_MONO 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define SRC_MONO_LBKGD 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define SRC_DSTCOLOR 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define BYTE_ORDER_MSB_TO_LSB 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define BYTE_ORDER_LSB_TO_MSB 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define DP_CONVERSION_TEMP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define HOST_BIG_ENDIAN_EN (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* DP_GUI_MASTER_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define GMC_SRC_CLIP_DEFAULT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define GMC_SRC_CLIP_LEAVE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define GMC_DST_CLIP_DEFAULT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define GMC_DST_CLIP_LEAVE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define GMC_BRUSH_8x8MONO 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define GMC_BRUSH_8x1MONO 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define GMC_BRUSH_1x8MONO 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define GMC_BRUSH_32x1MONO 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define GMC_BRUSH_32x32MONO 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define GMC_BRUSH_8x8COLOR 0x000000a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define GMC_BRUSH_8x1COLOR 0x000000b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define GMC_BRUSH_1x8COLOR 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define GMC_BRUSH_SOLID_COLOR 0x000000d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define GMC_DST_8BPP 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define GMC_DST_15BPP 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define GMC_DST_16BPP 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define GMC_DST_24BPP 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define GMC_DST_32BPP 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define GMC_DST_8BPP_RGB332 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define GMC_DST_8BPP_Y8 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define GMC_DST_8BPP_RGB8 0x00000900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define GMC_DST_16BPP_VYUY422 0x00000b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define GMC_DST_16BPP_YVYU422 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define GMC_DST_32BPP_AYUV444 0x00000e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define GMC_DST_16BPP_ARGB4444 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define GMC_SRC_MONO 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define GMC_SRC_MONO_LBKGD 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define GMC_SRC_DSTCOLOR 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define GMC_DP_CONVERSION_TEMP_9300 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define GMC_DP_CONVERSION_TEMP_6500 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define GMC_DP_SRC_RECT 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define GMC_DP_SRC_HOST 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define GMC_3D_FCN_EN_CLR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define GMC_3D_FCN_EN_SET 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define GMC_AUX_CLIP_LEAVE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define GMC_AUX_CLIP_CLEAR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define GMC_WRITE_MASK_LEAVE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define GMC_WRITE_MASK_SET 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define GMC_CLR_CMP_CNTL_DIS (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define GMC_SRC_DATATYPE_COLOR (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define ROP3_S 0x00cc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define ROP3_SRCCOPY 0x00cc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define ROP3_P 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define ROP3_PATCOPY 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define DP_SRC_SOURCE_MASK (7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define GMC_BRUSH_NONE (15 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define DP_SRC_SOURCE_MEMORY (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define GMC_BRUSH_SOLIDCOLOR 0x000000d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* DP_MIX bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define DP_SRC_RECT 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define DP_SRC_HOST 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define DP_SRC_HOST_BYTEALIGN 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* MPLL_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define MPLL_RESET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* MDLL_CKO bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define MCKOA_SLEEP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define MCKOA_RESET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define MCKOA_REF_SKEW_MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define MCKOA_FB_SKEW_MASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* MDLL_RDCKA bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define MRDCKA0_SLEEP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define MRDCKA0_RESET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define MRDCKA1_SLEEP 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define MRDCKA1_RESET 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* VCLK_ECP_CNTL constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define VCLK_SRC_SEL_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define VCLK_SRC_SEL_CPUCLK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define VCLK_SRC_SEL_PSCANCLK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define VCLK_SRC_SEL_BYTECLK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define VCLK_SRC_SEL_PPLLCLK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define PIXCLK_ALWAYS_ONb 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define PIXCLK_DAC_ALWAYS_ONb 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* BUS_CNTL1 constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define BUS_CNTL1_AGPCLK_VALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* PLL_PWRMGT_CNTL constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* TV_DAC_CNTL constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define TV_DAC_CNTL_BGSLEEP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define TV_DAC_CNTL_DETECT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define TV_DAC_CNTL_BGADJ__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define TV_DAC_CNTL_DACADJ__SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define TV_DAC_CNTL_RDACPD 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define TV_DAC_CNTL_GDACPD 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define TV_DAC_CNTL_BDACPD 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* DISP_MISC_CNTL constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* DISP_PWR_MAN constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define DISP_PWR_MAN_DISP_D3_RST (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define CNFG_MEMSIZE_MASK 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define MEM_CFG_TYPE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define DST_OFFSET_MASK 0x003fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define DST_PITCH_MASK 0x3fc00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define DEFAULT_TILE_MASK 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define PPLL_DIV_SEL_MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define PPLL_RESET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define PPLL_SLEEP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define PPLL_ATOMIC_UPDATE_EN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define PPLL_REF_DIV_MASK 0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define PPLL_FB3_DIV_MASK 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define PPLL_POST3_DIV_MASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define PPLL_ATOMIC_UPDATE_R 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define PPLL_ATOMIC_UPDATE_W 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define R300_PPLL_REF_DIV_ACC_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define GUI_ACTIVE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define MC_IND_INDEX 0x01F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define MC_IND_DATA 0x01FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* PAD_CTLR_STRENGTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define PAD_MANUAL_OVERRIDE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) // pllCLK_PIN_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define CLK_PIN_CNTL__OSC_EN 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define CLK_PIN_CNTL__CG_SPARE 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) // pllCLK_PWRMGT_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) // pllP2PLL_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define P2PLL_CNTL__P2PLL_RESET 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) // pllPIXCLKS_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) // pllPIXCLKS_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) // pllP2PLL_DIV_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) // pllSCLK_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define SCLK_CNTL__FORCE_DISP2 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define SCLK_CNTL__FORCE_CP 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define SCLK_CNTL__FORCE_HDP 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define SCLK_CNTL__FORCE_DISP1 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define SCLK_CNTL__FORCE_TOP 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define SCLK_CNTL__FORCE_E2 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define SCLK_CNTL__FORCE_SE 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define SCLK_CNTL__FORCE_IDCT 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define SCLK_CNTL__FORCE_VIP 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define SCLK_CNTL__FORCE_RE 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define SCLK_CNTL__FORCE_PB 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define SCLK_CNTL__FORCE_TAM 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define SCLK_CNTL__FORCE_TDM 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define SCLK_CNTL__FORCE_RB 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define SCLK_CNTL__FORCE_SUBPIC 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define SCLK_CNTL__FORCE_OV0 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define SCLK_CNTL__R300_FORCE_VAP (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define SCLK_CNTL__R300_FORCE_SR (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define SCLK_CNTL__R300_FORCE_PX (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define SCLK_CNTL__R300_FORCE_TX (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define SCLK_CNTL__R300_FORCE_US (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define SCLK_CNTL__R300_FORCE_SU (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define SCLK_CNTL__FORCEON_MASK 0xffff8000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) // pllSCLK_CNTL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define SCLK_CNTL2__R300_FORCE_TCL (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define SCLK_CNTL2__R300_FORCE_GA (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) // SCLK_MORE_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define SCLK_MORE_CNTL__FORCEON 0x00000700L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) // MCLK_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define MCLK_CNTL__FORCE_MCLKA 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define MCLK_CNTL__FORCE_MCLKB 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define MCLK_CNTL__FORCE_YCLKA 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define MCLK_CNTL__FORCE_YCLKB 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define MCLK_CNTL__FORCE_MC_MASK 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define MCLK_CNTL__FORCE_MC 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define MCLK_CNTL__FORCE_AIC 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) // MCLK_MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define MCLK_MISC__DLL_READY_LAT 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) // VCLK_ECP_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) // PLL_PWRMGT_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) // CLK_PWRMGT_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) // BUS_CNTL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define BUS_CNTL1__AGPCLK_VALID 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) // BUS_CNTL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) // CRTC_OFFSET_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) // CRTC_GEN_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) // CRTC2_GEN_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) // AGP_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define AGP_CNTL__EN_2X_STBB 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define AGP_CNTL__SBA_DIS_MASK 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define AGP_CNTL__SBA_DIS 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define AGP_CNTL__AGP_REV_ID 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define AGP_CNTL__FORCE_INT_VREF 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define AGP_CNTL__EN_RBFCALM 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define AGP_CNTL__DIS_RBF_MASK 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define AGP_CNTL__DIS_RBF 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) // AGP_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) // DISP_MISC_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) // DISP_PWR_MAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) // MC_IND_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) // MC_IND_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) // MC_CHP_IO_CNTL_A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) // MC_CHP_IO_CNTL_B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) // MC_CHP_IO_CNTL_A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) // MC_CHP_IO_CNTL_B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) // MEM_SDRAM_MODE_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) // MEM_SDRAM_MODE_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) // MEM_REFRESH_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) // MC_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define MC_STATUS__MC_IDLE_MASK 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define MC_STATUS__MC_IDLE 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) // MDLL_CKO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define MDLL_CKO__MCKOA_SLEEP 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define MDLL_CKO__MCKOA_RESET 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define MDLL_CKO__MCKOB_SLEEP 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define MDLL_CKO__MCKOB_RESET 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) // MDLL_RDCKA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) // MDLL_RDCKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define pllCLK_PIN_CNTL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define pllPPLL_CNTL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define pllPPLL_REF_DIV 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define pllPPLL_DIV_0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define pllPPLL_DIV_1 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define pllPPLL_DIV_2 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define pllPPLL_DIV_3 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #define pllVCLK_ECP_CNTL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define pllHTOTAL_CNTL 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define pllM_SPLL_REF_FB_DIV 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define pllAGP_PLL_CNTL 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define pllSPLL_CNTL 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define pllSCLK_CNTL 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define pllMPLL_CNTL 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #define pllMDLL_CKO 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define pllMDLL_RDCKA 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define pllMDLL_RDCKB 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define pllMCLK_CNTL 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define pllPLL_TEST_CNTL 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define pllCLK_PWRMGT_CNTL 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #define pllPLL_PWRMGT_CNTL 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define pllCG_TEST_MACRO_RW_WRITE 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define pllCG_TEST_MACRO_RW_READ 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define pllCG_TEST_MACRO_RW_DATA 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define pllCG_TEST_MACRO_RW_CNTL 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define pllDISP_TEST_MACRO_RW_WRITE 0x001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define pllDISP_TEST_MACRO_RW_READ 0x001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define pllDISP_TEST_MACRO_RW_DATA 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define pllDISP_TEST_MACRO_RW_CNTL 0x001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #define pllSCLK_CNTL2 0x001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define pllMCLK_MISC 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #define pllTV_PLL_FINE_CNTL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define pllTV_PLL_CNTL 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define pllTV_PLL_CNTL1 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define pllTV_DTO_INCREMENTS 0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define pllSPLL_AUX_CNTL 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define pllMPLL_AUX_CNTL 0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define pllP2PLL_CNTL 0x002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define pllP2PLL_REF_DIV 0x002B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define pllP2PLL_DIV_0 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define pllPIXCLKS_CNTL 0x002D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define pllHTOTAL2_CNTL 0x002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define pllSSPLL_CNTL 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define pllSSPLL_REF_DIV 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define pllSSPLL_DIV_0 0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define pllSS_INT_CNTL 0x0033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define pllSS_TST_CNTL 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define pllSCLK_MORE_CNTL 0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define ixMC_PERF_CNTL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define ixMC_PERF_SEL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define ixMC_PERF_REGION_0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define ixMC_PERF_REGION_1 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define ixMC_PERF_COUNT_0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define ixMC_PERF_COUNT_1 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define ixMC_PERF_COUNT_2 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define ixMC_PERF_COUNT_3 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define ixMC_PERF_COUNT_MEMCH_A 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define ixMC_PERF_COUNT_MEMCH_B 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define ixMC_IMP_CNTL 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define ixMC_CHP_IO_CNTL_A0 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define ixMC_CHP_IO_CNTL_A1 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define ixMC_CHP_IO_CNTL_B0 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define ixMC_CHP_IO_CNTL_B1 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define ixMC_IMP_CNTL_0 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define ixTC_MISMATCH_1 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define ixTC_MISMATCH_2 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #define ixMC_BIST_CTRL 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define ixREG_COLLAR_WRITE 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define ixREG_COLLAR_READ 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define ixR300_MC_IMP_CNTL 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define ixR300_MC_CHP_IO_CNTL_A0 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define ixR300_MC_CHP_IO_CNTL_A1 0x001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #define ixR300_MC_CHP_IO_CNTL_B0 0x001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define ixR300_MC_CHP_IO_CNTL_B1 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define ixR300_MC_CHP_IO_CNTL_C0 0x001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define ixR300_MC_CHP_IO_CNTL_C1 0x001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define ixR300_MC_CHP_IO_CNTL_D0 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #define ixR300_MC_CHP_IO_CNTL_D1 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define ixR300_MC_IMP_CNTL_0 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define ixR300_MC_ELPIDA_CNTL 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define ixR300_MC_READ_CNTL_CD 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define ixR300_MC_DEBUG_CNTL 0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define ixR300_MC_BIST_CNTL_0 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define ixR300_MC_BIST_CNTL_1 0x0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define ixR300_MC_BIST_CNTL_2 0x002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define ixR300_MC_BIST_CNTL_3 0x002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define ixR300_MC_BIST_CNTL_4 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define ixR300_MC_BIST_CNTL_5 0x002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define ixR300_MC_IMP_STATUS 0x002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define ixR300_MC_DLL_CNTL 0x002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define NB_TOM 0x15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #endif /* _RADEON_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags