^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2009 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __ASM_MACH_PXA168FB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __ASM_MACH_PXA168FB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Dumb interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PIN_MODE_DUMB_24 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PIN_MODE_DUMB_18_SPI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PIN_MODE_DUMB_18_GPIO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PIN_MODE_DUMB_16_SPI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PIN_MODE_DUMB_16_GPIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PIN_MODE_DUMB_12_SPI_GPIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PIN_MODE_SMART_18_SPI 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PIN_MODE_SMART_16_SPI 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIN_MODE_SMART_8_SPI_GPIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Dumb interface pin allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DUMB_MODE_RGB565 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DUMB_MODE_RGB565_UPPER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DUMB_MODE_RGB666 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DUMB_MODE_RGB666_UPPER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DUMB_MODE_RGB444 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DUMB_MODE_RGB444_UPPER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DUMB_MODE_RGB888 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* default fb buffer size WVGA-32bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DEFAULT_FB_SIZE (800 * 480 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Buffer pixel format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * bit0 is for rb swap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * bit12 is for Y UorV swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PIX_FMT_RGB565 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIX_FMT_BGR565 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIX_FMT_RGB1555 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PIX_FMT_BGR1555 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIX_FMT_RGB888PACK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PIX_FMT_BGR888PACK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PIX_FMT_RGB888UNPACK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PIX_FMT_BGR888UNPACK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PIX_FMT_RGBA888 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIX_FMT_BGRA888 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PIX_FMT_YUV422PACK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PIX_FMT_YVU422PACK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PIX_FMT_YUV422PLANAR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PIX_FMT_YVU422PLANAR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PIX_FMT_YUV420PLANAR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PIX_FMT_YVU420PLANAR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PIX_FMT_PSEUDOCOLOR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * PXA LCD controller private state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pxa168fb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dma_addr_t fb_start_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned is_blanked:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned panel_rbswap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * PXA fb machine information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct pxa168fb_mach_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) char id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct fb_videomode *modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Pix_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * I/O pin allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned io_pin_allocation_mode:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Dumb panel -- assignment of R/G/B component info to the 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * available external data lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned dumb_mode:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned panel_rgb_reverse_lanes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Dumb panel -- GPIO output data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned gpio_output_mask:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned gpio_output_data:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Dumb panel -- configurable output signal polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned invert_composite_blank:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned invert_pix_val_ena:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned invert_pixclock:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned panel_rbswap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned enable_lcd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif /* __ASM_MACH_PXA168FB_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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