Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *	linux/include/video/pmagb-b-fb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	TURBOchannel PMAGB-B Smart Frame Buffer (SFB) card support,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	Copyright (C) 1999, 2000, 2001 by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Michael Engel <engel@unix-ag.org> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	Karsten Merker <merker@linuxtag.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Copyright (c) 2005  Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *	Public License.  See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *	archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* IOmem resource offsets.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PMAGB_B_ROM		0x000000	/* REX option ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PMAGB_B_SFB		0x100000	/* SFB ASIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PMAGB_B_GP0		0x140000	/* general purpose output 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PMAGB_B_GP1		0x180000	/* general purpose output 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PMAGB_B_BT459		0x1c0000	/* Bt459 RAMDAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PMAGB_B_FBMEM		0x200000	/* frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PMAGB_B_SIZE		0x400000	/* address space size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* IOmem register offsets.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SFB_REG_VID_HOR		0x64		/* video horizontal setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SFB_REG_VID_VER		0x68		/* video vertical setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SFB_REG_VID_BASE	0x6c		/* video base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SFB_REG_TCCLK_COUNT	0x78		/* TURBOchannel clock count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SFB_REG_VIDCLK_COUNT	0x7c		/* video clock count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Video horizontal setup register constants.  All bits are r/w.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SFB_VID_HOR_BP_SHIFT	0x15		/* back porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SFB_VID_HOR_BP_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SFB_VID_HOR_SYN_SHIFT	0x0e		/* sync pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SFB_VID_HOR_SYN_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SFB_VID_HOR_FP_SHIFT	0x09		/* front porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SFB_VID_HOR_FP_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SFB_VID_HOR_PIX_SHIFT	0x00		/* active video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SFB_VID_HOR_PIX_MASK	0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Video vertical setup register constants.  All bits are r/w.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SFB_VID_VER_BP_SHIFT	0x16		/* back porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SFB_VID_VER_BP_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SFB_VID_VER_SYN_SHIFT	0x10		/* sync pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SFB_VID_VER_SYN_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SFB_VID_VER_FP_SHIFT	0x0b		/* front porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SFB_VID_VER_FP_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SFB_VID_VER_SL_SHIFT	0x00		/* active scan lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SFB_VID_VER_SL_MASK	0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Video base address register constants.  All bits are r/w.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SFB_VID_BASE_MASK	0x1ff		/* video base row address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Bt459 register offsets, byte-wide registers.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BT459_ADDR_LO		0x0		/* address low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BT459_ADDR_HI		0x4		/* address high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BT459_DATA		0x8		/* data window register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BT459_CMAP		0xc		/* color map window register */