^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __OMAPFB_DSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __OMAPFB_DSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_data/omapdss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DISPC_IRQ_FRAMEDONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DISPC_IRQ_VSYNC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DISPC_IRQ_GFX_END_WIN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DISPC_IRQ_OCP_ERR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DISPC_IRQ_VID1_END_WIN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DISPC_IRQ_VID2_END_WIN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DISPC_IRQ_SYNC_LOST (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DISPC_IRQ_WAKEUP (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DISPC_IRQ_VSYNC2 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DISPC_IRQ_VID3_END_WIN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DISPC_IRQ_FRAMEDONETV (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DISPC_IRQ_VSYNC3 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct omap_dss_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct omap_overlay_manager;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct dss_lcd_mgr_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct snd_aes_iec958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct snd_cea_861_aud_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct hdmi_avi_infoframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum omap_display_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) OMAP_DISPLAY_TYPE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) OMAP_DISPLAY_TYPE_DPI = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OMAP_DISPLAY_TYPE_DBI = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OMAP_DISPLAY_TYPE_SDI = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) OMAP_DISPLAY_TYPE_DSI = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) OMAP_DISPLAY_TYPE_VENC = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OMAP_DISPLAY_TYPE_DVI = 1 << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum omap_plane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OMAP_DSS_GFX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OMAP_DSS_VIDEO1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) OMAP_DSS_VIDEO2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) OMAP_DSS_VIDEO3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) OMAP_DSS_WB = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum omap_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) OMAP_DSS_CHANNEL_LCD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) OMAP_DSS_CHANNEL_DIGIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) OMAP_DSS_CHANNEL_LCD2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) OMAP_DSS_CHANNEL_LCD3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) OMAP_DSS_CHANNEL_WB = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum omap_color_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum omap_dss_load_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) OMAP_DSS_LOAD_CLUT_ONLY = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) OMAP_DSS_LOAD_FRAME_ONLY = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum omap_dss_trans_key_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) OMAP_DSS_COLOR_KEY_GFX_DST = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OMAP_DSS_COLOR_KEY_VID_SRC = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum omap_dss_signal_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) OMAPDSS_SIG_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) OMAPDSS_SIG_ACTIVE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum omap_dss_signal_edge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) OMAPDSS_DRIVE_SIG_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) OMAPDSS_DRIVE_SIG_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum omap_dss_venc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) OMAP_DSS_VENC_TYPE_COMPOSITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) OMAP_DSS_VENC_TYPE_SVIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) enum omap_dss_dsi_pixel_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) OMAP_DSS_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) OMAP_DSS_DSI_FMT_RGB666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OMAP_DSS_DSI_FMT_RGB666_PACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) OMAP_DSS_DSI_FMT_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum omap_dss_dsi_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) OMAP_DSS_DSI_CMD_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) OMAP_DSS_DSI_VIDEO_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum omap_display_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum omap_dss_display_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) OMAP_DSS_DISPLAY_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) OMAP_DSS_DISPLAY_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum omap_dss_rotation_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) OMAP_DSS_ROT_DMA = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) OMAP_DSS_ROT_VRFB = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) OMAP_DSS_ROT_TILER = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* clockwise rotation angle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum omap_dss_rotation_angle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) OMAP_DSS_ROT_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) OMAP_DSS_ROT_90 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) OMAP_DSS_ROT_180 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) OMAP_DSS_ROT_270 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum omap_overlay_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) OMAP_DSS_OVL_CAP_POS = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum omap_dss_output_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) OMAP_DSS_OUTPUT_DPI = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) OMAP_DSS_OUTPUT_DBI = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) OMAP_DSS_OUTPUT_SDI = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) OMAP_DSS_OUTPUT_VENC = 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) OMAP_DSS_OUTPUT_HDMI = 1 << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* DSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum omap_dss_dsi_trans_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Sync Pulses: both sync start and end packets sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) OMAP_DSS_DSI_PULSE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Sync Events: only sync start packets sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) OMAP_DSS_DSI_EVENT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Burst: only sync start packets sent, pixels are time compressed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) OMAP_DSS_DSI_BURST_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct omap_dss_dsi_videomode_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long hsclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned ndl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned bitspp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* DSI video mode blanking data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Unit: byte clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u16 hss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 hsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 hse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 hfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u16 hbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Unit: line clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 vsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u16 vfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 vbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* DSI blanking modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int blanking_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int hsa_blanking_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int hbp_blanking_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int hfp_blanking_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) enum omap_dss_dsi_trans_mode trans_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bool ddr_clk_always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int window_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct omap_dss_dsi_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum omap_dss_dsi_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enum omap_dss_dsi_pixel_format pixel_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct omap_video_timings *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long hs_clk_min, hs_clk_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long lp_clk_min, lp_clk_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) bool ddr_clk_always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) enum omap_dss_dsi_trans_mode trans_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct omap_video_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Unit: pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u16 x_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Unit: pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u16 y_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Unit: Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 pixelclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Unit: pixel clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u16 hsw; /* Horizontal synchronization pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Unit: pixel clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u16 hfp; /* Horizontal front porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Unit: pixel clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u16 hbp; /* Horizontal back porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Unit: line clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u16 vsw; /* Vertical synchronization pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Unit: line clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u16 vfp; /* Vertical front porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Unit: line clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u16 vbp; /* Vertical back porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Vsync logic level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) enum omap_dss_signal_level vsync_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Hsync logic level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) enum omap_dss_signal_level hsync_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Interlaced or Progressive timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bool interlace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Pixel clock edge to drive LCD data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum omap_dss_signal_edge data_pclk_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Data enable logic level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum omap_dss_signal_level de_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Pixel clock edges to drive HSYNC and VSYNC signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) enum omap_dss_signal_edge sync_pclk_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bool double_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Hardcoded timings for tv modes. Venc only uses these to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * identify the mode, and does not actually use the configs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * itself. However, the configs should be something that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * a normal monitor can also show */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) extern const struct omap_video_timings omap_dss_pal_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) extern const struct omap_video_timings omap_dss_ntsc_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct omap_dss_cpr_coefs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) s16 rr, rg, rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) s16 gr, gg, gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) s16 br, bg, bb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct omap_overlay_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dma_addr_t p_uv_addr; /* for NV12 format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u16 screen_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) enum omap_color_mode color_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 rotation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) enum omap_dss_rotation_type rotation_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bool mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u16 pos_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 pos_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u16 out_width; /* if 0, out_width == width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u16 out_height; /* if 0, out_height == height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 global_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 pre_mult_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 zorder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct omap_overlay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct kobject kobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* static fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) enum omap_plane id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) enum omap_color_mode supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) enum omap_overlay_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* dynamic fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct omap_overlay_manager *manager;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * The following functions do not block:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * is_enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * set_overlay_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * get_overlay_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * The rest of the functions may block and cannot be called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * interrupt context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int (*enable)(struct omap_overlay *ovl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int (*disable)(struct omap_overlay *ovl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bool (*is_enabled)(struct omap_overlay *ovl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int (*set_manager)(struct omap_overlay *ovl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct omap_overlay_manager *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int (*unset_manager)(struct omap_overlay *ovl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int (*set_overlay_info)(struct omap_overlay *ovl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct omap_overlay_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void (*get_overlay_info)(struct omap_overlay *ovl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct omap_overlay_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int (*wait_for_go)(struct omap_overlay *ovl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct omap_overlay_manager_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 default_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) enum omap_dss_trans_key_type trans_key_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 trans_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bool trans_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) bool partial_alpha_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bool cpr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct omap_dss_cpr_coefs cpr_coefs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct omap_overlay_manager {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct kobject kobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* static fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enum omap_channel id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct list_head overlays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) enum omap_display_type supported_displays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) enum omap_dss_output_id supported_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* dynamic fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct omap_dss_device *output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * The following functions do not block:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * set_manager_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * get_manager_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * The rest of the functions may block and cannot be called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * interrupt context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int (*set_output)(struct omap_overlay_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct omap_dss_device *output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int (*unset_output)(struct omap_overlay_manager *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int (*set_manager_info)(struct omap_overlay_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct omap_overlay_manager_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void (*get_manager_info)(struct omap_overlay_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct omap_overlay_manager_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int (*apply)(struct omap_overlay_manager *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int (*wait_for_go)(struct omap_overlay_manager *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* 22 pins means 1 clk lane and 10 data lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define OMAP_DSS_MAX_DSI_PINS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct omap_dsi_pin_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * pin numbers in the following order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * clk+, clk-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * data1+, data1-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * data2+, data2-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int pins[OMAP_DSS_MAX_DSI_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct omap_dss_writeback_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 p_uv_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u16 buf_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum omap_color_mode color_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 rotation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) enum omap_dss_rotation_type rotation_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bool mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u8 pre_mult_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct omapdss_dpi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int (*connect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void (*disconnect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int (*enable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) void (*disable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int (*check_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) void (*set_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) void (*get_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct omapdss_sdi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int (*connect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) void (*disconnect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int (*enable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void (*disable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int (*check_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void (*set_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void (*get_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct omapdss_dvi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int (*connect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void (*disconnect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int (*enable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void (*disable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int (*check_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) void (*set_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void (*get_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct omapdss_atv_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int (*connect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) void (*disconnect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int (*enable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void (*disable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int (*check_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void (*set_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) void (*get_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void (*set_type)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) enum omap_dss_venc_type type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) bool invert_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 (*get_wss)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct omapdss_hdmi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int (*connect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) void (*disconnect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int (*enable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void (*disable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int (*check_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void (*set_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) void (*get_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) bool (*detect)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int (*set_infoframe)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) const struct hdmi_avi_infoframe *avi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct omapdss_dsi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int (*connect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void (*disconnect)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct omap_dss_device *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int (*enable)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) bool enter_ulps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* bus configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int (*set_config)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) const struct omap_dss_dsi_config *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int (*configure_pins)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) const struct omap_dsi_pin_config *pin_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int (*update)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void (*callback)(int, void *), void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) void (*bus_lock)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void (*bus_unlock)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) void (*disable_video_output)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int vc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) void (*release_vc)(struct omap_dss_device *dssdev, int channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* data transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int (*gen_write)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int (*gen_read)(struct omap_dss_device *dssdev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 *reqdata, int reqlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int channel, u16 plen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct omap_dss_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct kobject kobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct list_head panel_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* alias in the form of "display%d" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) char alias[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) enum omap_display_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) enum omap_display_type output_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u8 data_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) } dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u8 datapairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } sdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) enum omap_dss_venc_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) bool invert_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } venc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) } phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct omap_video_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) enum omap_dss_dsi_pixel_format dsi_pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum omap_dss_dsi_mode dsi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u8 pixel_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* used to match device to driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const char *driver_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct omap_dss_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) const struct omapdss_dpi_ops *dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) const struct omapdss_sdi_ops *sdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) const struct omapdss_dvi_ops *dvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) const struct omapdss_hdmi_ops *hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) const struct omapdss_atv_ops *atv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) const struct omapdss_dsi_ops *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) } ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* helper variable for driver suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) bool activate_after_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) enum omap_display_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct omap_dss_device *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) enum omap_dss_display_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* OMAP DSS output specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* DISPC channel for this output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) enum omap_channel dispc_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) bool dispc_channel_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* output instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) enum omap_dss_output_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* the port number in the DT node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* dynamic fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct omap_overlay_manager *manager;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct omap_dss_device *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct omap_dss_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int (*probe)(struct omap_dss_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) void (*remove)(struct omap_dss_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int (*connect)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void (*disconnect)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int (*enable)(struct omap_dss_device *display);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) void (*disable)(struct omap_dss_device *display);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int (*run_test)(struct omap_dss_device *display, int test);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int (*update)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u16 x, u16 y, u16 w, u16 h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int (*sync)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int (*get_te)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 (*get_rotate)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) bool (*get_mirror)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int (*memory_read)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) void *buf, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u16 x, u16 y, u16 w, u16 h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) void (*get_resolution)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u16 *xres, u16 *yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) void (*get_dimensions)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 *width, u32 *height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int (*check_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) void (*set_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) void (*get_timings)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 (*get_wss)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) bool (*detect)(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) const struct hdmi_avi_infoframe *avi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #if IS_ENABLED(CONFIG_FB_OMAP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) enum omapdss_version omapdss_get_version(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) bool omapdss_is_initialized(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int omap_dss_register_driver(struct omap_dss_driver *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) void omap_dss_unregister_driver(struct omap_dss_driver *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int omapdss_register_display(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) void omapdss_unregister_display(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) void omap_dss_put_device(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct omap_dss_device *omap_dss_find_device(void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int (*match)(struct omap_dss_device *dssdev, void *data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) const char *omapdss_get_default_display_name(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) void videomode_to_omap_video_timings(const struct videomode *vm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct omap_video_timings *ovt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct videomode *vm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) int dss_feat_get_num_mgrs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int dss_feat_get_num_ovls(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int omap_dss_get_num_overlay_managers(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int omap_dss_get_num_overlays(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct omap_overlay *omap_dss_get_overlay(int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int omapdss_register_output(struct omap_dss_device *output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) void omapdss_unregister_output(struct omap_dss_device *output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct omap_dss_device *omap_dss_find_output(const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int omapdss_output_set_device(struct omap_dss_device *out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int omapdss_output_unset_device(struct omap_dss_device *out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u16 *xres, u16 *yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) void omapdss_default_get_timings(struct omap_dss_device *dssdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct omap_video_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int omapdss_compat_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) void omapdss_compat_uninit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return dssdev->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct device_node *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) omapdss_of_get_next_port(const struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct device_node *prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct device_node *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) omapdss_of_get_next_endpoint(const struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct device_node *prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct device_node *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) omapdss_of_get_first_endpoint(const struct device_node *parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct omap_dss_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) omapdss_of_find_source_for_first_ep(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static inline enum omapdss_version omapdss_get_version(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { return OMAPDSS_VER_UNKNOWN; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static inline bool omapdss_is_initialized(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) { return false; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static inline int omap_dispc_register_isr(omap_dispc_isr_t isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) void *arg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { return 0; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static inline int omap_dispc_unregister_isr(omap_dispc_isr_t isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) void *arg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { return 0; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static inline struct omap_dss_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) *omap_dss_get_device(struct omap_dss_device *dssdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) { return NULL; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static inline struct omap_dss_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) *omap_dss_get_next_device(struct omap_dss_device *from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {return NULL; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static inline void omap_dss_put_device(struct omap_dss_device *dssdev) {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static inline int omapdss_compat_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) { return 0; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static inline void omapdss_compat_uninit(void) {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static inline int omap_dss_get_num_overlay_managers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { return 0; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static inline struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { return NULL; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static inline int omap_dss_get_num_overlays(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { return 0; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static inline struct omap_overlay *omap_dss_get_overlay(int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { return NULL; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #endif /* FB_OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #endif /* __OMAPFB_DSS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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