^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * newport.h: Defines and register layout for NEWPORT graphics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ulf Carlsson - Compatibility with the IRIX structures added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _SGI_NEWPORT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _SGI_NEWPORT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) typedef volatile unsigned int npireg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) union npfloat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) volatile float flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) npireg_t word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) typedef union npfloat npfreg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) union np_dcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) npireg_t byword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct { volatile unsigned short s0, s1; } byshort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct { volatile unsigned char b0, b1, b2, b3; } bybytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct newport_rexregs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) npireg_t drawmode1; /* GL extra mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DM1_PLANES 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DM1_NOPLANES 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DM1_RGBPLANES 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DM1_RGBAPLANES 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DM1_OLAYPLANES 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DM1_PUPPLANES 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DM1_CIDPLANES 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPORT_DMODE1_DDMASK 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NPORT_DMODE1_DD4 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPORT_DMODE1_DD8 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPORT_DMODE1_DD12 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPORT_DMODE1_DD24 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NPORT_DMODE1_DSRC 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NPORT_DMODE1_YFLIP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NPORT_DMODE1_RWPCKD 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NPORT_DMODE1_HDMASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NPORT_DMODE1_HD4 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NPORT_DMODE1_HD8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NPORT_DMODE1_HD12 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NPORT_DMODE1_HD32 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NPORT_DMODE1_RWDBL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NPORT_DMODE1_CCMASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NPORT_DMODE1_CCLT 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NPORT_DMODE1_CCEQ 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NPORT_DMODE1_CCGT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NPORT_DMODE1_RGBMD 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define NPORT_DMODE1_SFMASK 0x00380000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define NPORT_DMODE1_SF0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NPORT_DMODE1_SF1 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NPORT_DMODE1_SFDC 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NPORT_DMODE1_SFMDC 0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NPORT_DMODE1_SFSA 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NPORT_DMODE1_SFMSA 0x00280000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NPORT_DMODE1_DFMASK 0x01c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NPORT_DMODE1_DF0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NPORT_DMODE1_DF1 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NPORT_DMODE1_DFSC 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NPORT_DMODE1_DFMSC 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NPORT_DMODE1_DFSA 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NPORT_DMODE1_DFMSA 0x01400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NPORT_DMODE1_LOMASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NPORT_DMODE1_LOZERO 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NPORT_DMODE1_LOAND 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NPORT_DMODE1_LOANDR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NPORT_DMODE1_LOSRC 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define NPORT_DMODE1_LOANDI 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NPORT_DMODE1_LODST 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NPORT_DMODE1_LOXOR 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NPORT_DMODE1_LOOR 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NPORT_DMODE1_LONOR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NPORT_DMODE1_LOXNOR 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NPORT_DMODE1_LONDST 0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NPORT_DMODE1_LOORR 0xb0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NPORT_DMODE1_LONSRC 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NPORT_DMODE1_LOORI 0xd0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NPORT_DMODE1_LONAND 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NPORT_DMODE1_LOONE 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) npireg_t drawmode0; /* REX command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* These bits define the graphics opcode being performed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NPORT_DMODE0_NOP 0x00000000 /* No operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NPORT_DMODE0_RD 0x00000001 /* Read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* The following decide what addressing mode(s) are to be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* And now some misc. operation control bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define NPORT_DMODE0_DOSETUP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NPORT_DMODE0_CHOST 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NPORT_DMODE0_AHOST 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NPORT_DMODE0_STOPX 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NPORT_DMODE0_STOPY 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define NPORT_DMODE0_SK1ST 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NPORT_DMODE0_SKLST 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NPORT_DMODE0_ZPENAB 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define NPORT_DMODE0_LISPENAB 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NPORT_DMODE0_LISLST 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define NPORT_DMODE0_L32 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define NPORT_DMODE0_ZOPQ 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define NPORT_DMODE0_LISOPQ 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define NPORT_DMODE0_SHADE 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define NPORT_DMODE0_LRONLY 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NPORT_DMODE0_XYOFF 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define NPORT_DMODE0_CLAMP 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define NPORT_DMODE0_ENDPF 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NPORT_DMODE0_YSTR 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) npireg_t lsmode; /* Mode for line stipple ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) npireg_t lspattern; /* Pattern for line stipple ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) npireg_t lspatsave; /* Backup save pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) npireg_t zpattern; /* Pixel zpattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) npireg_t colorback; /* Background color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) npireg_t colorvram; /* Clear color for fast vram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) npireg_t alpharef; /* Reference value for afunctions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) npireg_t smask0x; /* Window GL relative screen mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) npireg_t smask0y; /* Window GL relative screen mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) npireg_t _setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) npireg_t _stepz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) npireg_t _lsrestore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) npireg_t _lssave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int _pad1[0x30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Iterators, full state for context switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) npfreg_t _xstart; /* X-start point (current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) npfreg_t _ystart; /* Y-start point (current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) npfreg_t _xend; /* x-end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) npfreg_t _yend; /* y-end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) npfreg_t bresd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) npfreg_t bress1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) npireg_t bresoctinc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) volatile int bresrndinc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) npireg_t brese1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) npireg_t bress2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) npireg_t aweight0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) npireg_t aweight1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) npfreg_t xstartf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) npfreg_t ystartf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) npfreg_t xendf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) npfreg_t yendf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) npireg_t xstarti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) npfreg_t xendf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) npireg_t xystarti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) npireg_t xyendi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) npireg_t xstartendi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int _unused2[0x29];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) npfreg_t colorred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) npfreg_t coloralpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) npfreg_t colorgrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) npfreg_t colorblue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) npfreg_t slopered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) npfreg_t slopealpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) npfreg_t slopegrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) npfreg_t slopeblue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) npireg_t wrmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) npireg_t colori;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) npfreg_t colorx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) npfreg_t slopered1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) npireg_t hostrw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) npireg_t hostrw1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) npireg_t dcbmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define NPORT_DMODE_WMASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define NPORT_DMODE_W4 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define NPORT_DMODE_W1 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define NPORT_DMODE_W2 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define NPORT_DMODE_W3 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define NPORT_DMODE_EDPACK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define NPORT_DMODE_ECINC 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define NPORT_DMODE_CMASK 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define NPORT_DMODE_AMASK 0x00000780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define NPORT_DMODE_AVC2 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define NPORT_DMODE_ACMALL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define NPORT_DMODE_ACM0 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define NPORT_DMODE_ACM1 0x00000180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define NPORT_DMODE_AXMALL 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define NPORT_DMODE_AXM0 0x00000280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define NPORT_DMODE_AXM1 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define NPORT_DMODE_ABT 0x00000380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define NPORT_DMODE_AVCC1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define NPORT_DMODE_AVAB1 0x00000480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define NPORT_DMODE_ALG3V0 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define NPORT_DMODE_A1562 0x00000580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NPORT_DMODE_ESACK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define NPORT_DMODE_EASACK 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define NPORT_DMODE_CWMASK 0x0003e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define NPORT_DMODE_CHMASK 0x007c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define NPORT_DMODE_CSMASK 0x0f800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define NPORT_DMODE_SENDIAN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int _unused3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) union np_dcb dcbdata0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) npireg_t dcbdata1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct newport_cregs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) npireg_t smask1x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) npireg_t smask1y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) npireg_t smask2x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) npireg_t smask2y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) npireg_t smask3x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) npireg_t smask3y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) npireg_t smask4x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) npireg_t smask4y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) npireg_t topscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) npireg_t xywin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) npireg_t clipmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define NPORT_CMODE_SM0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define NPORT_CMODE_SM1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define NPORT_CMODE_SM2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define NPORT_CMODE_SM3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define NPORT_CMODE_SM4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define NPORT_CMODE_CMSK 0x00001e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int _unused0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define NPORT_CFG_G32MD 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define NPORT_CFG_BWIDTH 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define NPORT_CFG_ERCVR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define NPORT_CFG_BDMSK 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define NPORT_CFG_BFAINT 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define NPORT_CFG_GDMSK 0x00001f80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define NPORT_CFG_GD0 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define NPORT_CFG_GD1 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define NPORT_CFG_GD2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define NPORT_CFG_GD3 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define NPORT_CFG_GD4 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define NPORT_CFG_GFAINT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define NPORT_CFG_TOMSK 0x0001c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define NPORT_CFG_VRMSK 0x000e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define NPORT_CFG_FBTYP 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) npireg_t _unused1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) npireg_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define NPORT_STAT_VERS 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define NPORT_STAT_GBUSY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define NPORT_STAT_BBUSY 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define NPORT_STAT_VRINT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define NPORT_STAT_VIDINT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define NPORT_STAT_GLMSK 0x00001f80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define NPORT_STAT_BLMSK 0x0007e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define NPORT_STAT_BFIRQ 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define NPORT_STAT_GFIRQ 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) npireg_t ustatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) npireg_t dcbreset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct newport_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct newport_rexregs set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int _unused0[0x16e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct newport_rexregs go;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int _unused1[0x22e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct newport_cregs cset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int _unused2[0x1ef];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct newport_cregs cgo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int drawmode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int drawmode0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int lsmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int lspattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int lspatsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int zpattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int colorback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int colorvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int alpharef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int smask0x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int smask0y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int _xstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int _ystart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int _xend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int _yend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int xymove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int bresd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int bress1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int bresoctinc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int bresrndinc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int brese1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int bress2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int aweight0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int aweight1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int colorred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int coloralpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int colorgrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int colorblue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int slopered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int slopealpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned int slopegrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int slopeblue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int wrmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int hostrw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int hostrw1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* configregs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int smask1x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int smask1y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int smask2x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int smask2y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int smask3x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int smask3y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int smask4x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int smask4y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int topscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned int xywin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int clipmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* dcb registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int dcbmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned int dcbdata0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int dcbdata1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } newport_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Reading/writing VC2 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define VC2_REGADDR_INDEX 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define VC2_REGADDR_IREG 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define VC2_REGADDR_RAM 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define VC2_VLINET_ADDR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define VC2_VFRAMET_ADDR 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define VC2_CGLYPH_ADDR 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Now the Indexed registers of the VC2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define VC2_IREG_VENTRY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define VC2_IREG_CENTRY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define VC2_IREG_CURSX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define VC2_IREG_CURSY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define VC2_IREG_CCURSX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define VC2_IREG_DENTRY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define VC2_IREG_SLEN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define VC2_IREG_RADDR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define VC2_IREG_VFPTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define VC2_IREG_VLSPTR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define VC2_IREG_VLIR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define VC2_IREG_VLCTR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define VC2_IREG_CTPTR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define VC2_IREG_WCURSY 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define VC2_IREG_DFPTR 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define VC2_IREG_DLTPTR 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define VC2_IREG_CONTROL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define VC2_IREG_CONFIG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline void newport_vc2_set(struct newport_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned char vc2ireg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) NPORT_DMODE_ECINC | VC2_PROTOCOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static inline unsigned short newport_vc2_get(struct newport_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned char vc2ireg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) NPORT_DMODE_ECINC | VC2_PROTOCOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) regs->set.dcbdata0.bybytes.b3 = vc2ireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) NPORT_DMODE_ECINC | VC2_PROTOCOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return regs->set.dcbdata0.byshort.s1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* VC2 Control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define VC2_CTRL_EVIRQ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define VC2_CTRL_EDISP 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define VC2_CTRL_EVIDEO 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define VC2_CTRL_EDIDS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define VC2_CTRL_ECURS 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define VC2_CTRL_EGSYNC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define VC2_CTRL_EILACE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define VC2_CTRL_ECDISP 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define VC2_CTRL_ECCURS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define VC2_CTRL_ECG64 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define VC2_CTRL_GLSEL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Controlling the color map on NEWPORT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define NCMAP_REGADDR_AREG 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define NCMAP_REGADDR_ALO 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define NCMAP_REGADDR_AHI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define NCMAP_REGADDR_PBUF 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define NCMAP_REGADDR_CREG 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define NCMAP_REGADDR_SREG 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define NCMAP_REGADDR_RREG 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static __inline__ void newport_cmap_setaddr(struct newport_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned short addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) NCMAP_REGADDR_AREG | NPORT_DMODE_W2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) regs->set.dcbdata0.byshort.s1 = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) NCMAP_REGADDR_PBUF | NPORT_DMODE_W3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static __inline__ void newport_cmap_setrgb(struct newport_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned char red,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned char green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned char blue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) regs->set.dcbdata0.byword =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) (red << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) (green << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (blue << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Miscellaneous NEWPORT routines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define BUSY_TIMEOUT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static __inline__ int newport_wait(struct newport_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int t = BUSY_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) while (--t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!(regs->cset.status & NPORT_STAT_GBUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return !t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static __inline__ int newport_bfwait(struct newport_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int t = BUSY_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) while (--t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if(!(regs->cset.status & NPORT_STAT_BBUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return !t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * DCBMODE register defines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Width of the data being transferred for each DCBDATA[01] word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define DCB_DATAWIDTH_4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define DCB_DATAWIDTH_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define DCB_DATAWIDTH_2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DCB_DATAWIDTH_3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DCB_ENDATAPACK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Enables DCBCRS auto increment after each DCB transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DCB_ENCRSINC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* shift for accessing the control register select address (DBCCRS, 3 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DCB_CRS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* DCBADDR (4 bits): display bus slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DCB_ADDR_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DCB_VC2 (0 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DCB_CMAP0 (2 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DCB_CMAP1 (3 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DCB_XMAP0 (5 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DCB_XMAP1 (6 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DCB_BT445 (7 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define DCB_VCC1 (8 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define DCB_VAB1 (9 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define DCB_RESERVED (15 << DCB_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* DCB protocol ack types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DCB_ENSYNCACK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define DCB_ENASYNCACK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DCB_CSWIDTH_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DCB_CSHOLD_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define DCB_CSSETUP_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* XMAP9 specific defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* XMAP9 -- registers as seen on the DCBMODE register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) # define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) # define XM9_PUPMODE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) # define XM9_ODD_PIXEL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) # define XM9_8_BITPLANES (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) # define XM9_SLOW_DCB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) # define XM9_VIDEO_RGBMAP_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) # define XM9_EXPRESS_VIDEO (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) # define XM9_VIDEO_OPTION (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) # define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) # define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) # define XM9_FIFO_0_AVAIL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) # define XM9_FIFO_1_AVAIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) # define XM9_FIFO_2_AVAIL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) # define XM9_FIFO_3_AVAIL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) # define XM9_FIFO_FULL XM9_FIFO_0_AVAIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) # define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) # define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) # define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) # define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) # define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DCB_CYCLES(setup,hold,width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ((hold << DCB_CSHOLD_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) (setup << DCB_CSSETUP_SHIFT)| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (width << DCB_CSWIDTH_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) xmap9FIFOWait (struct newport_regs *rex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) newport_bfwait (rex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (cfreq > 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else if (cfreq > 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define BT445_PROTOCOL DCB_CYCLES(1,1,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define BT445_REVISION_REG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif /* !(_SGI_NEWPORT_H) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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