^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/include/video/neo_reg.h -- NeoMagic Framebuffer Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Public License. See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define NEO_BS0_BLT_BUSY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define NEO_BS0_FIFO_AVAIL 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NEO_BS0_FIFO_PEND 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NEO_BC0_DST_Y_DEC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NEO_BC0_X_DEC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NEO_BC0_SRC_TRANS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NEO_BC0_SRC_IS_FG 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NEO_BC0_SRC_Y_DEC 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NEO_BC0_FILL_PAT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NEO_BC0_SRC_MONO 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NEO_BC0_SYS_TO_VID 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NEO_BC1_DEPTH8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NEO_BC1_DEPTH16 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NEO_BC1_X_320 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NEO_BC1_X_640 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NEO_BC1_X_800 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NEO_BC1_X_1024 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NEO_BC1_X_1152 0x00001400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NEO_BC1_X_1280 0x00001800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NEO_BC1_X_1600 0x00001c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NEO_BC1_DST_TRANS 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NEO_BC1_MSTR_BLT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NEO_BC1_FILTER_Z 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NEO_BC2_WR_TR_DST 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NEO_BC3_SRC_XY_ADDR 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NEO_BC3_DST_XY_ADDR 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NEO_BC3_CLIP_ON 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NEO_BC3_FIFO_EN 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NEO_BC3_BLT_ON_ADDR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NEO_BC3_SKIP_MAPPING 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NEO_MODE1_DEPTH8 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NEO_MODE1_DEPTH16 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NEO_MODE1_DEPTH24 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NEO_MODE1_X_320 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NEO_MODE1_X_640 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NEO_MODE1_X_800 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NEO_MODE1_X_1024 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NEO_MODE1_X_1152 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NEO_MODE1_X_1280 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NEO_MODE1_X_1600 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NEO_MODE1_BLT_ON_ADDR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* These are offseted in MMIO space by par->CursorOff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NEOREG_CURSCNTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NEOREG_CURSX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NEOREG_CURSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NEOREG_CURSBGCOLOR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NEOREG_CURSFGCOLOR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NEOREG_CURSMEMPOS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define NEO_CURS_DISABLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NEO_CURS_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NEO_ICON64_ENABLE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NEO_ICON128_ENABLE 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NEO_ICON_BLANK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NEO_GR01_SUPPRESS_VSYNC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NEO_GR01_SUPPRESS_HSYNC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifdef NEOFB_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) # define DBG(x) printk (KERN_DEBUG "neofb: %s\n", (x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define DBG(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCI_CHIP_NM2070 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCI_CHIP_NM2090 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCI_CHIP_NM2093 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCI_CHIP_NM2097 0x0083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCI_CHIP_NM2160 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCI_CHIP_NM2200 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCI_CHIP_NM2230 0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCI_CHIP_NM2360 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCI_CHIP_NM2380 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) typedef volatile struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __u32 bltStat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __u32 bltCntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __u32 xpColor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __u32 fgColor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 bgColor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __u32 pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __u32 clipLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __u32 clipRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __u32 srcBitOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __u32 srcStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __u32 reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __u32 dstStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __u32 xyExt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __u32 reserved1[19];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __u32 pageCntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __u32 pageBase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __u32 postBase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __u32 postPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __u32 dataPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } Neo2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MMIO_SIZE 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NEO_EXT_CR_MAX 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NEO_EXT_GR_MAX 0xC7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct neofb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct vgastate state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned char MiscOutReg; /* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned char CRTC[25]; /* Crtc Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned char Sequencer[5]; /* Video Sequencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned char Graphics[9]; /* Video Graphics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned char Attribute[21]; /* Video Attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned char GeneralLockReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned char ExtCRTDispAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned char ExtCRTOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned char SysIfaceCntl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned char SysIfaceCntl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned char ExtColorModeSelect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned char biosMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char PanelDispCntlReg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned char PanelDispCntlReg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned char PanelDispCntlReg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned char PanelDispCntlRegRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned char PanelVertCenterReg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned char PanelVertCenterReg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned char PanelVertCenterReg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned char PanelVertCenterReg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned char PanelVertCenterReg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned char PanelHorizCenterReg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned char PanelHorizCenterReg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned char PanelHorizCenterReg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned char PanelHorizCenterReg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned char PanelHorizCenterReg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ProgramVCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned char VCLK3NumeratorLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned char VCLK3NumeratorHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned char VCLK3Denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned char VerticalExt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 __iomem *mmio_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 cursorOff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 *cursorPad; /* Must die !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) Neo2200 __iomem *neo2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Panels size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int NeoPanelWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int NeoPanelHeight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int maxClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int pci_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int lcd_stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int internal_display;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int external_display;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int libretto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int x_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int y_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } biosMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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