^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/include/video/mmp_disp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Header file for Marvell MMP Display Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Marvell Technology Group Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Zhou Zhu <zzhu3@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MMP_DISP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MMP_DISP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PIXFMT_UYVY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PIXFMT_VYUY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PIXFMT_YUYV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PIXFMT_YUV422P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PIXFMT_YVU422P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PIXFMT_YUV420P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PIXFMT_YVU420P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PIXFMT_RGB565 = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PIXFMT_BGR565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PIXFMT_RGB1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PIXFMT_BGR1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PIXFMT_RGB888PACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PIXFMT_BGR888PACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PIXFMT_RGB888UNPACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PIXFMT_BGR888UNPACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PIXFMT_RGBA888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PIXFMT_BGRA888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PIXFMT_RGB666, /* for output usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PIXFMT_PSEUDOCOLOR = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline int pixfmt_to_stride(int pix_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) switch (pix_fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case PIXFMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case PIXFMT_BGR565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case PIXFMT_RGB1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) case PIXFMT_BGR1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case PIXFMT_UYVY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case PIXFMT_VYUY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case PIXFMT_YUYV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case PIXFMT_RGB888UNPACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case PIXFMT_BGR888UNPACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case PIXFMT_RGBA888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case PIXFMT_BGRA888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case PIXFMT_RGB888PACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case PIXFMT_BGR888PACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case PIXFMT_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case PIXFMT_YVU422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) case PIXFMT_YUV420P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case PIXFMT_YVU420P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case PIXFMT_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* parameters used by path/overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* overlay related para: win/addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct mmp_win {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* position/size of window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u16 xsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u16 ysrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u16 xdst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 ydst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 xpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 ypos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u16 left_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 right_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 up_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u16 bottom_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * pitch[0]: graphics/video layer line length or y pitch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * pitch[1]/pitch[2]: video u/v pitch if non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 pitch[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mmp_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* phys address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 phys[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* path related para: mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mmp_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 hsync_invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 vsync_invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 invert_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 pixclock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int pix_fmt_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* main structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mmp_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct mmp_overlay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct mmp_panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* status types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MMP_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MMP_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline const char *stat_name(int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case MMP_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return "OFF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case MMP_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return "ON";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return "UNKNOWNSTAT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mmp_overlay_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* should be provided by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void (*set_fetch)(struct mmp_overlay *overlay, int fetch_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void (*set_onoff)(struct mmp_overlay *overlay, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void (*set_win)(struct mmp_overlay *overlay, struct mmp_win *win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int (*set_addr)(struct mmp_overlay *overlay, struct mmp_addr *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* overlay describes a z-order indexed slot in each path. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mmp_overlay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mmp_path *path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* overlay info: private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int dmafetch_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct mmp_addr addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mmp_win win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int open_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct mutex access_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mmp_overlay_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* panel type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PANELTYPE_ACTIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PANELTYPE_SMART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PANELTYPE_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PANELTYPE_DSI_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PANELTYPE_DSI_VIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mmp_panel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* use node to register to list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* path name used to connect to proper path configed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *plat_path_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int panel_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void *plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int (*get_modelist)(struct mmp_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct mmp_mode **modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void (*set_mode)(struct mmp_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct mmp_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void (*set_onoff)(struct mmp_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct mmp_path_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int (*check_status)(struct mmp_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct mmp_overlay *(*get_overlay)(struct mmp_path *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int overlay_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int (*get_modelist)(struct mmp_path *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mmp_mode **modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* follow ops should be provided by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void (*set_onoff)(struct mmp_path *path, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* todo: add query */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* path output types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PATH_OUT_PARALLEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PATH_OUT_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PATH_OUT_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* path is main part of mmp-disp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct mmp_path {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* use node to register to list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* init data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int output_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct mmp_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void *plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* dynamic use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mmp_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int open_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct mutex access_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct mmp_path_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* layers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int overlay_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct mmp_overlay overlays[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) extern struct mmp_path *mmp_get_path(const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline void mmp_path_set_mode(struct mmp_path *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct mmp_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) path->ops.set_mode(path, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static inline void mmp_path_set_onoff(struct mmp_path *path, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) path->ops.set_onoff(path, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline int mmp_path_get_modelist(struct mmp_path *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct mmp_mode **modelist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return path->ops.get_modelist(path, modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline struct mmp_overlay *mmp_path_get_overlay(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mmp_path *path, int overlay_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return path->ops.get_overlay(path, overlay_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline void mmp_overlay_set_fetch(struct mmp_overlay *overlay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int fetch_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (overlay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) overlay->ops->set_fetch(overlay, fetch_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline void mmp_overlay_set_onoff(struct mmp_overlay *overlay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (overlay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) overlay->ops->set_onoff(overlay, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static inline void mmp_overlay_set_win(struct mmp_overlay *overlay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct mmp_win *win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (overlay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) overlay->ops->set_win(overlay, win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static inline int mmp_overlay_set_addr(struct mmp_overlay *overlay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct mmp_addr *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (overlay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return overlay->ops->set_addr(overlay, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * driver data is set from each detailed ctrl driver for path usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * it defined a common interface that plat driver need to implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct mmp_path_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* driver data, set when registed*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int output_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int overlay_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) void (*set_onoff)(struct mmp_path *path, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct mmp_overlay_ops *overlay_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void *plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) extern struct mmp_path *mmp_register_path(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mmp_path_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) extern void mmp_unregister_path(struct mmp_path *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) extern void mmp_register_panel(struct mmp_panel *panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) extern void mmp_unregister_panel(struct mmp_panel *panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* defintions for platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* interface for buffer driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct mmp_buffer_driver_mach_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const char *path_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int overlay_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int dmafetch_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int default_pixfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* interface for controllers driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct mmp_mach_path_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int overlay_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int output_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 path_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 link_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 dsi_rbswap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct mmp_mach_plat_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int path_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct mmp_mach_path_config *paths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* interface for panel drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct mmp_mach_panel_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void (*plat_set_onoff)(int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) const char *plat_path_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif /* _MMP_DISP_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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