Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *      linux/drivers/video/maxinefb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *      DECstation 5000/xx onboard framebuffer support, Copyright (C) 1999 by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *      Michael Engel <engel@unix-ag.org> and Karsten Merker <merker@guug.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *      This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *      Public License.  See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *      archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * IMS332 video controller register base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAXINEFB_IMS332_ADDRESS		KSEG1ADDR(0x1c140000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * Begin of DECstation 5000/xx onboard framebuffer memory, default resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * is 1024x768x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DS5000_xx_ONBOARD_FBMEM_START	KSEG1ADDR(0x0a000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *      The IMS 332 video controller used in the DECstation 5000/xx series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *      uses 32 bits wide registers; the following defines declare the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  *      register numbers, to get the real offset, these have to be multiplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *      by four.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMS332_REG_CURSOR_RAM           0x200	/* hardware cursor bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * The color palette entries have the form 0x00BBGGRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMS332_REG_COLOR_PALETTE        0x100	/* color palette, 256 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMS332_REG_CURSOR_COLOR_PALETTE	0x0a1	/* cursor color palette, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 						/* 3 entries             */