^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2005-2009 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The code contained herein is licensed under the GNU Lesser General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Public License. You may obtain a copy of the GNU Lesser General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Public License Version 2.1 or later at the following locations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * http://www.opensource.org/licenses/lgpl-license.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * http://www.gnu.org/copyleft/lgpl.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DRM_IPU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DRM_IPU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <video/videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct ipu_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum ipuv3_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) IPUV3EX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) IPUV3M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) IPUV3H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Bitfield of Display Interface signal polarities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ipu_di_signal_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned data_pol:1; /* true = inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned clk_pol:1; /* true = rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned enable_pol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct videomode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 v_to_h_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IPU_DI_CLKMODE_SYNC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IPU_DI_CLKMODE_EXT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long clkflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 hsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 vsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Enumeration of CSI destinations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum ipu_csi_dest {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IPU_CSI_DEST_IC, /* to Image Converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IPU_CSI_DEST_VDIC, /* to VDIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Enumeration of IPU rotation modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IPU_ROT_BIT_VFLIP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IPU_ROT_BIT_HFLIP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IPU_ROT_BIT_90 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum ipu_rotate_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IPU_ROTATE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* 90-degree rotations require the IRT unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum ipu_color_space {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) IPUV3_COLORSPACE_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) IPUV3_COLORSPACE_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) IPUV3_COLORSPACE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Enumeration of VDI MOTION select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum ipu_motion_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MOTION_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) LOW_MOTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MED_MOTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) HIGH_MOTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ipuv3_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum ipu_channel_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IPU_IRQ_EOF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) IPU_IRQ_NFACK = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) IPU_IRQ_NFB4EOF = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) IPU_IRQ_EOS = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Enumeration of IDMAC channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IPUV3_CHANNEL_CSI0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IPUV3_CHANNEL_CSI1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IPUV3_CHANNEL_CSI2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IPUV3_CHANNEL_CSI3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * but the direct CSI->VDI linking is handled the same way as IDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * these channel names are used to support the direct CSI->VDI link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IPUV3_CHANNEL_CSI_DIRECT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IPUV3_CHANNEL_CSI_VDI_PREV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IPUV3_CHANNEL_MEM_VDI_PREV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IPUV3_CHANNEL_MEM_VDI_CUR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IPUV3_CHANNEL_MEM_VDI_NEXT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IPUV3_CHANNEL_MEM_IC_PP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IPUV3_CHANNEL_VDI_MEM_RECENT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IPUV3_CHANNEL_G_MEM_IC_PP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IPUV3_CHANNEL_IC_PP_MEM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IPUV3_CHANNEL_MEM_BG_SYNC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IPUV3_CHANNEL_MEM_BG_ASYNC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IPUV3_CHANNEL_MEM_FG_SYNC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IPUV3_CHANNEL_MEM_DC_SYNC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IPUV3_CHANNEL_MEM_FG_ASYNC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IPUV3_CHANNEL_DC_MEM_READ 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IPUV3_CHANNEL_MEM_DC_ASYNC 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IPUV3_CHANNEL_MEM_DC_COMMAND 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IPUV3_CHANNEL_MEM_ROT_ENC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IPUV3_CHANNEL_MEM_ROT_VF 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IPUV3_CHANNEL_MEM_ROT_PP 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IPUV3_CHANNEL_ROT_ENC_MEM 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IPUV3_CHANNEL_ROT_VF_MEM 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IPUV3_CHANNEL_ROT_PP_MEM 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IPUV3_NUM_CHANNELS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline int ipu_channel_alpha_channel(int ch_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (ch_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case IPUV3_CHANNEL_G_MEM_IC_PP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case IPUV3_CHANNEL_MEM_FG_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case IPUV3_CHANNEL_MEM_FG_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case IPUV3_CHANNEL_MEM_BG_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case IPUV3_CHANNEL_MEM_BG_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ipu_map_irq(struct ipu_soc *ipu, int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum ipu_channel_irq irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IPU_IRQ_DP_SF_START (448 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IPU_IRQ_DP_SF_END (448 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IPU_IRQ_DC_FC_0 (448 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IPU_IRQ_DC_FC_1 (448 + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IPU_IRQ_DC_FC_2 (448 + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IPU_IRQ_DC_FC_3 (448 + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IPU_IRQ_DC_FC_4 (448 + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IPU_IRQ_DC_FC_6 (448 + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * IPU Common functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ipu_get_num(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void ipu_dump(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * IPU Image DMA Controller (idmac) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void ipu_idmac_put(struct ipuv3_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) bool doublebuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * IPU Channel Parameter Memory (cpmem) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct ipu_rgb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct fb_bitfield red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct fb_bitfield green;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct fb_bitfield blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct fb_bitfield transp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ipu_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct v4l2_pix_format pix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct v4l2_rect rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dma_addr_t phys0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dma_addr_t phys1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* chroma plane offset overrides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 u_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 v_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void ipu_cpmem_zero(struct ipuv3_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) enum ipu_rotate_mode rot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const struct ipu_rgb *rgb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int uv_stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int u_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int v_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void ipu_cpmem_dump(struct ipuv3_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * IPU Display Controller (dc) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct ipu_dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct ipu_di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void ipu_dc_put(struct ipu_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 pixel_fmt, u32 width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void ipu_dc_enable(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void ipu_dc_enable_channel(struct ipu_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void ipu_dc_disable_channel(struct ipu_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void ipu_dc_disable(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * IPU Display Interface (di) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void ipu_di_put(struct ipu_di *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ipu_di_disable(struct ipu_di *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ipu_di_enable(struct ipu_di *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ipu_di_get_num(struct ipu_di *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * IPU Display Multi FIFO Controller (dmfc) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct dmfc_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void ipu_dmfc_put(struct dmfc_channel *dmfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * IPU Display Processor (dp) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IPU_DP_FLOW_SYNC_BG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IPU_DP_FLOW_SYNC_FG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IPU_DP_FLOW_ASYNC0_BG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IPU_DP_FLOW_ASYNC0_FG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IPU_DP_FLOW_ASYNC1_BG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IPU_DP_FLOW_ASYNC1_FG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void ipu_dp_put(struct ipu_dp *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int ipu_dp_enable(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ipu_dp_enable_channel(struct ipu_dp *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void ipu_dp_disable(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ipu_dp_setup_channel(struct ipu_dp *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) enum ipu_color_space in, enum ipu_color_space out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) bool bg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * IPU Prefetch Resolve Gasket (prg) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int ipu_prg_max_active_channels(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bool ipu_prg_present(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) uint64_t modifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int ipu_prg_enable(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void ipu_prg_disable(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int axi_id, unsigned int width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int height, unsigned int stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 format, uint64_t modifier, unsigned long *eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * IPU CMOS Sensor Interface (csi) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct ipu_csi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ipu_csi_init_interface(struct ipu_csi *csi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const struct v4l2_mbus_config *mbus_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const struct v4l2_mbus_framefmt *infmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) const struct v4l2_mbus_framefmt *outfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) bool ipu_csi_is_interlaced(struct ipu_csi *csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 r_value, u32 g_value, u32 b_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 pix_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct v4l2_mbus_framefmt *mbus_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 max_ratio, u32 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ipu_csi_enable(struct ipu_csi *csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ipu_csi_disable(struct ipu_csi *csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void ipu_csi_put(struct ipu_csi *csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void ipu_csi_dump(struct ipu_csi *csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * IPU Image Converter (ic) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) enum ipu_ic_task {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) IC_TASK_ENCODER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) IC_TASK_VIEWFINDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) IC_TASK_POST_PROCESSOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) IC_NUM_TASKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * The parameters that describe a colorspace according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Image Converter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * - Y'CbCr encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * - quantization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * - "colorspace" (RGB or YUV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct ipu_ic_colorspace {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) enum v4l2_ycbcr_encoding enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enum v4l2_quantization quant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) enum ipu_color_space cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ipu_ic_fill_colorspace(struct ipu_ic_colorspace *ic_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) enum v4l2_ycbcr_encoding enc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) enum v4l2_quantization quant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum ipu_color_space cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ic_cs->enc = enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ic_cs->quant = quant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ic_cs->cs = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct ipu_ic_csc_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) s16 coeff[3][3]; /* signed 9-bit integer coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) s16 offset[3]; /* signed 11+2-bit fixed point offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 scale:2; /* scale coefficients * 2^(scale-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ipu_ic_csc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct ipu_ic_colorspace in_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct ipu_ic_colorspace out_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct ipu_ic_csc_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct ipu_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int __ipu_ic_calc_csc(struct ipu_ic_csc *csc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ipu_ic_calc_csc(struct ipu_ic_csc *csc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) enum v4l2_ycbcr_encoding in_enc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) enum v4l2_quantization in_quant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) enum ipu_color_space in_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) enum v4l2_ycbcr_encoding out_enc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum v4l2_quantization out_quant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) enum ipu_color_space out_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int ipu_ic_task_init(struct ipu_ic *ic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) const struct ipu_ic_csc *csc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int in_width, int in_height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int out_width, int out_height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int ipu_ic_task_init_rsc(struct ipu_ic *ic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) const struct ipu_ic_csc *csc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int in_width, int in_height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int out_width, int out_height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 rsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int ipu_ic_task_graphics_init(struct ipu_ic *ic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) const struct ipu_ic_colorspace *g_in_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bool galpha_en, u32 galpha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) bool colorkey_en, u32 colorkey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) void ipu_ic_task_enable(struct ipu_ic *ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) void ipu_ic_task_disable(struct ipu_ic *ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 width, u32 height, int burst_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) enum ipu_rotate_mode rot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int ipu_ic_enable(struct ipu_ic *ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int ipu_ic_disable(struct ipu_ic *ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) void ipu_ic_put(struct ipu_ic *ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) void ipu_ic_dump(struct ipu_ic *ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * IPU Video De-Interlacer (vdi) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct ipu_vdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) void ipu_vdi_unsetup(struct ipu_vdi *vdi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int ipu_vdi_enable(struct ipu_vdi *vdi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int ipu_vdi_disable(struct ipu_vdi *vdi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) void ipu_vdi_put(struct ipu_vdi *vdi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * IPU Sensor Multiple FIFO Controller (SMFC) functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void ipu_smfc_put(struct ipu_smfc *smfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int ipu_smfc_enable(struct ipu_smfc *smfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int ipu_smfc_disable(struct ipu_smfc *smfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) bool hflip, bool vflip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) bool hflip, bool vflip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct ipu_client_platformdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int csi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int dma[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #endif /* __DRM_IPU_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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