Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * include/video/gbe.h -- SGI GBE (Graphics Back End)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1999 Silicon Graphics, Inc. (Jeffrey Newquist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __GBE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __GBE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) struct sgi_gbe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	volatile uint32_t ctrlstat;	/* general control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	volatile uint32_t dotclock;	/* dot clock PLL control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	volatile uint32_t i2c;		/* crt I2C control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	volatile uint32_t sysclk;	/* system clock PLL control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	volatile uint32_t i2cfp;	/* flat panel I2C control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	volatile uint32_t id;		/* device id/chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	volatile uint32_t config;       /* power on configuration [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	volatile uint32_t bist;         /* internal bist status [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	uint32_t _pad0[0x010000/4 - 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	volatile uint32_t vt_xy;	/* current dot coords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	volatile uint32_t vt_xymax;	/* maximum dot coords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	volatile uint32_t vt_vsync;	/* vsync on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	volatile uint32_t vt_hsync;	/* hsync on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	volatile uint32_t vt_vblank;	/* vblank on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	volatile uint32_t vt_hblank;	/* hblank on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	volatile uint32_t vt_flags;	/* polarity of vt signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	volatile uint32_t vt_f2rf_lock;	/* f2rf & framelck y coord */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	volatile uint32_t vt_intr01;	/* intr 0,1 y coords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	volatile uint32_t vt_intr23;	/* intr 2,3 y coords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	volatile uint32_t fp_hdrv;	/* flat panel hdrv on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	volatile uint32_t fp_vdrv;	/* flat panel vdrv on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	volatile uint32_t fp_de;	/* flat panel de on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	volatile uint32_t vt_hpixen;	/* intrnl horiz pixel on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	volatile uint32_t vt_vpixen;	/* intrnl vert pixel on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	volatile uint32_t vt_hcmap;	/* cmap write (horiz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	volatile uint32_t vt_vcmap;	/* cmap write (vert) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	volatile uint32_t did_start_xy;	/* eol/f did/xy reset val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	volatile uint32_t crs_start_xy;	/* eol/f crs/xy reset val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	volatile uint32_t vc_start_xy;	/* eol/f vc/xy reset val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	uint32_t _pad1[0xffb0/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	volatile uint32_t ovr_inhwctrl;	/* overlay plane ctrl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	volatile uint32_t ovr_control;	/* overlay plane ctrl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	uint32_t _pad2[0xfff4/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	volatile uint32_t frm_size_pixel;/*normal plane ctrl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	volatile uint32_t frm_inhwctrl;	/* normal plane ctrl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	volatile uint32_t frm_control;	/* normal plane ctrl 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	uint32_t _pad3[0xfff0/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	volatile uint32_t did_inhwctrl;	/* DID control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	volatile uint32_t did_control;	/* DID shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	uint32_t _pad4[0x7ff8/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	volatile uint32_t mode_regs[32];/* WID table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	uint32_t _pad5[0x7f80/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	volatile uint32_t cmap[6144];	/* color map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	uint32_t _pad6[0x2000/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	volatile uint32_t cm_fifo;	/* color map fifo status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	uint32_t _pad7[0x7ffc/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	volatile uint32_t gmap[256];	/* gamma map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	uint32_t _pad8[0x7c00/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	volatile uint32_t gmap10[1024];	/* gamma map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	uint32_t _pad9[0x7000/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	volatile uint32_t crs_pos;	/* cusror control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	volatile uint32_t crs_ctl;	/* cusror control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	volatile uint32_t crs_cmap[3];	/* crs cmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	uint32_t _pad10[0x7fec/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	volatile uint32_t crs_glyph[64];/* crs glyph */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	uint32_t _pad11[0x7f00/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	volatile uint32_t vc_0;	/* video capture crtl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	volatile uint32_t vc_1;	/* video capture crtl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	volatile uint32_t vc_2;	/* video capture crtl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	volatile uint32_t vc_3;	/* video capture crtl 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	volatile uint32_t vc_4;	/* video capture crtl 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	volatile uint32_t vc_5;	/* video capture crtl 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	volatile uint32_t vc_6;	/* video capture crtl 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	volatile uint32_t vc_7;	/* video capture crtl 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	volatile uint32_t vc_8;	/* video capture crtl 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MASK(msb, lsb)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GET(v, msb, lsb)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SET(v, f, msb, lsb)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GET_GBE_FIELD(reg, field, v)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SET_GBE_FIELD(reg, field, v, f)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * Bit mask information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GBE_CTRLSTAT_CHIPID_MSB		 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define GBE_CTRLSTAT_CHIPID_LSB		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define GBE_CTRLSTAT_SENSE_N_MSB	 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define GBE_CTRLSTAT_SENSE_N_LSB	 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GBE_CTRLSTAT_PCLKSEL_MSB	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GBE_CTRLSTAT_PCLKSEL_LSB	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GBE_DOTCLK_M_MSB		 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GBE_DOTCLK_M_LSB		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GBE_DOTCLK_N_MSB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GBE_DOTCLK_N_LSB		 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GBE_DOTCLK_P_MSB		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GBE_DOTCLK_P_LSB		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GBE_DOTCLK_RUN_MSB		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GBE_DOTCLK_RUN_LSB		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GBE_VT_XY_Y_MSB		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GBE_VT_XY_Y_LSB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GBE_VT_XY_X_MSB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GBE_VT_XY_X_LSB		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GBE_VT_XY_FREEZE_MSB		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GBE_VT_XY_FREEZE_LSB		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GBE_FP_VDRV_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GBE_FP_VDRV_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GBE_FP_VDRV_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GBE_FP_VDRV_OFF_LSB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GBE_FP_HDRV_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GBE_FP_HDRV_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GBE_FP_HDRV_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GBE_FP_HDRV_OFF_LSB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GBE_FP_DE_ON_MSB		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GBE_FP_DE_ON_LSB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GBE_FP_DE_OFF_MSB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GBE_FP_DE_OFF_LSB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GBE_VT_VSYNC_VSYNC_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GBE_VT_VSYNC_VSYNC_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GBE_VT_VSYNC_VSYNC_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GBE_VT_VSYNC_VSYNC_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GBE_VT_HSYNC_HSYNC_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GBE_VT_HSYNC_HSYNC_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GBE_VT_HSYNC_HSYNC_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GBE_VT_HSYNC_HSYNC_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GBE_VT_VBLANK_VBLANK_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GBE_VT_VBLANK_VBLANK_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GBE_VT_VBLANK_VBLANK_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GBE_VT_VBLANK_VBLANK_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GBE_VT_HBLANK_HBLANK_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GBE_VT_HBLANK_HBLANK_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GBE_VT_HBLANK_HBLANK_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GBE_VT_HBLANK_HBLANK_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GBE_VT_FLAGS_F2RF_HIGH_MSB	 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GBE_VT_FLAGS_F2RF_HIGH_LSB	 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GBE_VT_FLAGS_SYNC_LOW_MSB	 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GBE_VT_FLAGS_SYNC_LOW_LSB	 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GBE_VT_FLAGS_SYNC_HIGH_MSB	 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GBE_VT_FLAGS_SYNC_HIGH_LSB	 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GBE_VT_FLAGS_HDRV_LOW_MSB	 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GBE_VT_FLAGS_HDRV_LOW_LSB	 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GBE_VT_FLAGS_HDRV_INVERT_MSB	 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GBE_VT_FLAGS_HDRV_INVERT_LSB	 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GBE_VT_FLAGS_VDRV_LOW_MSB	 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GBE_VT_FLAGS_VDRV_LOW_LSB	 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GBE_VT_FLAGS_VDRV_INVERT_MSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GBE_VT_FLAGS_VDRV_INVERT_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GBE_VT_VCMAP_VCMAP_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GBE_VT_VCMAP_VCMAP_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GBE_VT_VCMAP_VCMAP_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GBE_VT_VCMAP_VCMAP_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GBE_VT_HCMAP_HCMAP_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GBE_VT_HCMAP_HCMAP_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GBE_VT_HCMAP_HCMAP_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GBE_VT_HCMAP_HCMAP_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GBE_VT_XYMAX_MAXX_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GBE_VT_XYMAX_MAXX_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GBE_VT_XYMAX_MAXY_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GBE_VT_XYMAX_MAXY_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GBE_VT_HPIXEN_HPIXEN_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GBE_VT_HPIXEN_HPIXEN_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GBE_VT_HPIXEN_HPIXEN_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GBE_VT_HPIXEN_HPIXEN_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GBE_VT_VPIXEN_VPIXEN_ON_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GBE_VT_VPIXEN_VPIXEN_ON_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GBE_VT_VPIXEN_VPIXEN_OFF_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GBE_VT_VPIXEN_VPIXEN_OFF_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GBE_FRM_CONTROL_FRM_TILE_PTR_MSB	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GBE_FRM_CONTROL_FRM_TILE_PTR_LSB	 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GBE_FRM_CONTROL_FRM_LINEAR_MSB		 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GBE_FRM_CONTROL_FRM_LINEAR_LSB		 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB	 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GBE_FRM_SIZE_TILE_FRM_RHS_MSB		 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GBE_FRM_SIZE_TILE_FRM_RHS_LSB		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GBE_FRM_SIZE_TILE_FRM_DEPTH_MSB		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GBE_FRM_SIZE_TILE_FRM_DEPTH_LSB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GBE_DID_CONTROL_DID_DMA_ENABLE_MSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GBE_DID_CONTROL_DID_DMA_ENABLE_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GBE_DID_START_XY_DID_STARTY_MSB		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GBE_DID_START_XY_DID_STARTY_LSB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GBE_DID_START_XY_DID_STARTX_MSB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GBE_DID_START_XY_DID_STARTX_LSB		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GBE_CRS_START_XY_CRS_STARTY_MSB		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GBE_CRS_START_XY_CRS_STARTY_LSB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GBE_CRS_START_XY_CRS_STARTX_MSB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GBE_CRS_START_XY_CRS_STARTX_LSB		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GBE_WID_AUX_MSB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GBE_WID_AUX_LSB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GBE_WID_GAMMA_MSB	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GBE_WID_GAMMA_LSB	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GBE_WID_CM_MSB		 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GBE_WID_CM_LSB		 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GBE_WID_TYP_MSB		 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GBE_WID_TYP_LSB		 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GBE_WID_BUF_MSB		 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GBE_WID_BUF_LSB		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GBE_VC_START_XY_VC_STARTY_MSB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GBE_VC_START_XY_VC_STARTY_LSB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GBE_VC_START_XY_VC_STARTX_MSB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GBE_VC_START_XY_VC_STARTX_LSB	 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GBE_FRM_DEPTH_8		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GBE_FRM_DEPTH_16	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define GBE_FRM_DEPTH_32	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GBE_CMODE_I8		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GBE_CMODE_I12		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GBE_CMODE_RG3B2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GBE_CMODE_RGB4		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GBE_CMODE_ARGB5		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GBE_CMODE_RGB8		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define GBE_CMODE_RGBA5		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GBE_CMODE_RGB10		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define GBE_BMODE_BOTH		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GBE_CRS_MAGIC		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define GBE_PIXEN_MAGIC_ON	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GBE_PIXEN_MAGIC_OFF	 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GBE_TLB_SIZE		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* [1] - only GBE revision 2 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * Video Timing Data Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct gbe_timing_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	short width;		/* Monitor resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	short height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	int fields_sec;		/* fields/sec  (Hz -3 dec. places */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	int cfreq;		/* pixel clock frequency (MHz -3 dec. places) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	short htotal;		/* Horizontal total pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	short hblank_start;	/* Horizontal blank start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	short hblank_end;	/* Horizontal blank end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	short hsync_start;	/* Horizontal sync start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	short hsync_end;	/* Horizontal sync end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	short vtotal;		/* Vertical total lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	short vblank_start;	/* Vertical blank start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	short vblank_end;	/* Vertical blank end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	short vsync_start;	/* Vertical sync start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	short vsync_end;	/* Vertical sync end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	short pll_m;		/* PLL M parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	short pll_n;		/* PLL P parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	short pll_p;		/* PLL N parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Defines for gbe_vof_info_t flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define GBE_VOF_UNKNOWNMON	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GBE_VOF_STEREO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GBE_VOF_DO_GENSYNC	4	/* enable incoming sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GBE_VOF_SYNC_ON_GREEN	8	/* sync on green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define GBE_VOF_FLATPANEL	0x1000	/* FLATPANEL Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define GBE_VOF_MAGICKEY	0x2000	/* Backdoor key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif		/* ! __GBE_H__ */