Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * --------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * --------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * License.  See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef CVISIONPPC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CVISIONPPC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef PM2FB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pm2fb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct cvppc_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	unsigned char* pci_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	unsigned char* pci_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u32 user_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CSPPC_PCI_BRIDGE		0xfffe0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CSPPC_BRIDGE_ENDIAN		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CSPPC_BRIDGE_INT		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define	CVPPC_PCI_CONFIG		0xfffc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CVPPC_ROM_ADDRESS		0xe2000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CVPPC_REGS_REGION		0xef000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CVPPC_FB_APERTURE_ONE		0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CVPPC_FB_APERTURE_TWO		0xe1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CVPPC_FB_SIZE			0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CVPPC_MEM_CONFIG_OLD		0xed61fcaa	/* FIXME Fujitsu?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CVPPC_MEM_CONFIG_NEW		0xed41c532	/* FIXME USA?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CVPPC_MEMCLOCK			83000		/* in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* CVPPC_BRIDGE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CSPPCF_BRIDGE_BIG_ENDIAN	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* CVPPC_BRIDGE_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CSPPCF_BRIDGE_ACTIVE_INT2	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif	/* CVISIONPPC_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * That's all folks!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  *****************************************************************************/