^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/video/clgenfb.h - Cirrus Logic chipset constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Original clgenfb author: Frank Neumann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on retz3fb.c and clgen.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1997 Jes Sorensen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1996 Frank Neumann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ***************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Format this code with GNU indent '-kr -i8 -pcs' options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifndef __CLGENFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define __CLGENFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* OLD COMMENT: these definitions might most of the time also work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* OLD COMMENT: for other CL-GD542x/543x based boards.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*** External/General Registers ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CL_POS102 0x102 /* POS102 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CL_VSSM 0x46e8 /* Adapter Sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CL_VSSM2 0x3c3 /* Motherboard Sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*** VGA Sequencer Registers ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* the following are from the "extension registers" group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CL_SEQR6 0x6 /* Unlock ALL Extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CL_SEQR7 0x7 /* Extended Sequencer Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CL_SEQR8 0x8 /* EEPROM Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CL_SEQRB 0xb /* VCLK0 Numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CL_SEQRC 0xc /* VCLK1 Numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CL_SEQRD 0xd /* VCLK2 Numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CL_SEQRE 0xe /* VCLK3 Numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CL_SEQRF 0xf /* DRAM Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CL_SEQR10 0x10 /* Graphics Cursor X Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CL_SEQR11 0x11 /* Graphics Cursor Y Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CL_SEQR12 0x12 /* Graphics Cursor Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*** CRT Controller Registers ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* the following are from the "extension registers" group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CL_CRT19 0x19 /* Interlace End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CL_CRT1A 0x1a /* Interlace Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CL_CRT1B 0x1b /* Extended Display Controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CL_CRT1C 0x1c /* Sync adjust and genlock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CL_CRT1D 0x1d /* Overlay Extended Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CL_CRT1E 0x1e /* Another overflow register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CL_CRT25 0x25 /* Part Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CL_CRT27 0x27 /* ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CL_CRT51 0x51 /* P4 disable "flicker fixer" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*** Graphics Controller Registers ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* the following are from the "extension registers" group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CL_GR9 0x9 /* Offset Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CL_GRA 0xa /* Offset Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CL_GRB 0xb /* Graphics Controller Mode Extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CL_GRF 0xf /* Display Compression Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CL_GR12 0x12 /* Background Color Byte 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CL_GR13 0x13 /* Foreground Color Byte 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CL_GR14 0x14 /* Background Color Byte 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CL_GR15 0x15 /* Foreground Color Byte 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* the following are CL-GD5426/'28 specific blitter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CL_GR20 0x20 /* BLT Width Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CL_GR21 0x21 /* BLT Width High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CL_GR22 0x22 /* BLT Height Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CL_GR23 0x23 /* BLT Height High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CL_GR24 0x24 /* BLT Destination Pitch Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CL_GR25 0x25 /* BLT Destination Pitch High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CL_GR26 0x26 /* BLT Source Pitch Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CL_GR27 0x27 /* BLT Source Pitch High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CL_GR28 0x28 /* BLT Destination Start Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CL_GR29 0x29 /* BLT Destination Start Mid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CL_GR2A 0x2a /* BLT Destination Start High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CL_GR2C 0x2c /* BLT Source Start Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CL_GR2D 0x2d /* BLT Source Start Mid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CL_GR2E 0x2e /* BLT Source Start High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CL_GR30 0x30 /* BLT Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CL_GR31 0x31 /* BLT Start/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CL_GR32 0x32 /* BLT Raster Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CL_GR33 0x33 /* another P4 "compat" register.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CL_GR34 0x34 /* Transparent Color Select Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CL_GR35 0x35 /* Transparent Color Select High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CL_GR38 0x38 /* Source Transparent Color Mask Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CL_GR39 0x39 /* Source Transparent Color Mask High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*** Attribute Controller Registers ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CL_AR34 0x34 /* TEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif /* __CLGENFB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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