Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*  $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/drivers/video/aty128.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Register definitions for ATI Rage128 boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Anthony Tong <atong@uiuc.edu>, 1999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Brad Douglas <brad@neruo.com>, 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef REG_RAGE128_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define REG_RAGE128_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLOCK_CNTL_INDEX			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLOCK_CNTL_DATA				0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define BIOS_0_SCRATCH				0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define BUS_CNTL				0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define BUS_CNTL1				0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define GEN_INT_CNTL				0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CRTC_GEN_CNTL				0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CRTC_EXT_CNTL				0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DAC_CNTL				0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define I2C_CNTL_1				0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PALETTE_INDEX				0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PALETTE_DATA				0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CNFG_CNTL				0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GEN_RESET_CNTL				0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CNFG_MEMSIZE				0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MEM_CNTL				0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MEM_POWER_MISC				0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AGP_BASE				0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AGP_CNTL				0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AGP_APER_OFFSET				0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PCI_GART_PAGE				0x017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PC_NGUI_MODE				0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PC_NGUI_CTLSTAT				0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MPP_TB_CONFIG				0x01C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MPP_GP_CONFIG				0x01C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define VIPH_CONTROL				0x01D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CRTC_H_TOTAL_DISP			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CRTC_H_SYNC_STRT_WID			0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CRTC_V_TOTAL_DISP			0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CRTC_V_SYNC_STRT_WID			0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CRTC_VLINE_CRNT_VLINE			0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CRTC_CRNT_FRAME				0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CRTC_GUI_TRIG_VLINE			0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CRTC_OFFSET				0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CRTC_OFFSET_CNTL			0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CRTC_PITCH				0x022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OVR_CLR					0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OVR_WID_LEFT_RIGHT			0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OVR_WID_TOP_BOTTOM			0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define LVDS_GEN_CNTL				0x02d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DDA_CONFIG				0x02e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DDA_ON_OFF				0x02e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VGA_DDA_CONFIG				0x02e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define VGA_DDA_ON_OFF				0x02ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CRTC2_H_TOTAL_DISP			0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CRTC2_H_SYNC_STRT_WID			0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CRTC2_V_TOTAL_DISP			0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CRTC2_V_SYNC_STRT_WID			0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CRTC2_VLINE_CRNT_VLINE			0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CRTC2_CRNT_FRAME			0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CRTC2_GUI_TRIG_VLINE			0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CRTC2_OFFSET				0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CRTC2_OFFSET_CNTL			0x0328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CRTC2_PITCH				0x032c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DDA2_CONFIG				0x03e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DDA2_ON_OFF				0x03e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CRTC2_GEN_CNTL				0x03f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CRTC2_STATUS				0x03fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OV0_SCALE_CNTL				0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SUBPIC_CNTL				0x0540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PM4_BUFFER_OFFSET			0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PM4_BUFFER_CNTL				0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PM4_BUFFER_WM_CNTL			0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PM4_BUFFER_DL_RPTR_ADDR			0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PM4_BUFFER_DL_RPTR			0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PM4_BUFFER_DL_WPTR			0x0714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PM4_VC_FPU_SETUP			0x071c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PM4_FPU_CNTL				0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PM4_VC_FORMAT				0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PM4_VC_CNTL				0x0728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PM4_VC_I01				0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PM4_VC_VLOFF				0x0730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PM4_VC_VLSIZE				0x0734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PM4_IW_INDOFF				0x0738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PM4_IW_INDSIZE				0x073c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PM4_FPU_FPX0				0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PM4_FPU_FPY0				0x0744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define PM4_FPU_FPX1				0x0748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define PM4_FPU_FPY1				0x074c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define PM4_FPU_FPX2				0x0750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PM4_FPU_FPY2				0x0754
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PM4_FPU_FPY3				0x0758
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PM4_FPU_FPY4				0x075c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PM4_FPU_FPY5				0x0760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PM4_FPU_FPY6				0x0764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PM4_FPU_FPR				0x0768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PM4_FPU_FPG				0x076c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PM4_FPU_FPB				0x0770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PM4_FPU_FPA				0x0774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PM4_FPU_INTXY0				0x0780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PM4_FPU_INTXY1				0x0784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PM4_FPU_INTXY2				0x0788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PM4_FPU_INTARGB				0x078c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PM4_FPU_FPTWICEAREA			0x0790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PM4_FPU_DMAJOR01			0x0794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PM4_FPU_DMAJOR12			0x0798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PM4_FPU_DMAJOR02			0x079c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PM4_FPU_STAT				0x07a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PM4_STAT				0x07b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PM4_TEST_CNTL				0x07d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PM4_MICROCODE_ADDR			0x07d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PM4_MICROCODE_RADDR			0x07d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PM4_MICROCODE_DATAH			0x07dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PM4_MICROCODE_DATAL			0x07e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PM4_CMDFIFO_ADDR			0x07e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PM4_CMDFIFO_DATAH			0x07e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PM4_CMDFIFO_DATAL			0x07ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PM4_BUFFER_ADDR				0x07f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PM4_BUFFER_DATAH			0x07f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PM4_BUFFER_DATAL			0x07f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PM4_MICRO_CNTL				0x07fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CAP0_TRIG_CNTL				0x0950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CAP1_TRIG_CNTL				0x09c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *                  GUI Block Memory Mapped Registers                         *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *                     These registers are FIFOed.                            *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PM4_FIFO_DATA_EVEN			0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PM4_FIFO_DATA_ODD			0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DST_OFFSET				0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DST_PITCH				0x1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DST_WIDTH				0x140c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DST_HEIGHT				0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SRC_X					0x1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SRC_Y					0x1418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DST_X					0x141c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DST_Y					0x1420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SRC_PITCH_OFFSET			0x1428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DST_PITCH_OFFSET			0x142c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SRC_Y_X					0x1434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DST_Y_X					0x1438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DST_HEIGHT_WIDTH			0x143c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DP_GUI_MASTER_CNTL			0x146c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BRUSH_SCALE				0x1470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BRUSH_Y_X				0x1474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DP_BRUSH_BKGD_CLR			0x1478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DP_BRUSH_FRGD_CLR			0x147c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DST_WIDTH_X				0x1588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DST_HEIGHT_WIDTH_8			0x158c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SRC_X_Y					0x1590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DST_X_Y					0x1594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DST_WIDTH_HEIGHT			0x1598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DST_WIDTH_X_INCY			0x159c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DST_HEIGHT_Y				0x15a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DST_X_SUB				0x15a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DST_Y_SUB				0x15a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SRC_OFFSET				0x15ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SRC_PITCH				0x15b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DST_HEIGHT_WIDTH_BW			0x15b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLR_CMP_CNTL				0x15c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLR_CMP_CLR_SRC				0x15c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLR_CMP_CLR_DST				0x15c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLR_CMP_MASK				0x15cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DP_SRC_FRGD_CLR				0x15d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DP_SRC_BKGD_CLR				0x15dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DST_BRES_ERR				0x1628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DST_BRES_INC				0x162c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DST_BRES_DEC				0x1630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DST_BRES_LNTH				0x1634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DST_BRES_LNTH_SUB			0x1638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SC_LEFT					0x1640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SC_RIGHT				0x1644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SC_TOP					0x1648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SC_BOTTOM				0x164c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SRC_SC_RIGHT				0x1654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SRC_SC_BOTTOM				0x165c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GUI_DEBUG0				0x16a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GUI_DEBUG1				0x16a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GUI_TIMEOUT				0x16b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GUI_TIMEOUT0				0x16b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GUI_TIMEOUT1				0x16b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GUI_PROBE				0x16bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DP_CNTL					0x16c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DP_DATATYPE				0x16c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DP_MIX					0x16c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DP_WRITE_MASK				0x16cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DP_CNTL_XDIR_YDIR_YMAJOR		0x16d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DEFAULT_OFFSET				0x16e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DEFAULT_PITCH				0x16e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DEFAULT_SC_BOTTOM_RIGHT			0x16e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SC_TOP_LEFT				0x16ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SC_BOTTOM_RIGHT				0x16f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SRC_SC_BOTTOM_RIGHT			0x16f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define WAIT_UNTIL				0x1720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CACHE_CNTL				0x1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GUI_STAT				0x1740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PC_GUI_MODE				0x1744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PC_GUI_CTLSTAT				0x1748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PC_DEBUG_MODE				0x1760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BRES_DST_ERR_DEC			0x1780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TRAIL_BRES_T12_ERR_DEC			0x1784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TRAIL_BRES_T12_INC			0x1788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DP_T12_CNTL				0x178c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DST_BRES_T1_LNTH			0x1790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DST_BRES_T2_LNTH			0x1794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SCALE_SRC_HEIGHT_WIDTH			0x1994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SCALE_OFFSET_0				0x1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SCALE_PITCH				0x199c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SCALE_X_INC				0x19a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SCALE_Y_INC				0x19a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SCALE_HACC				0x19a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SCALE_VACC				0x19ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SCALE_DST_X_Y				0x19b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SCALE_DST_HEIGHT_WIDTH			0x19b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SCALE_3D_CNTL				0x1a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SCALE_3D_DATATYPE			0x1a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SETUP_CNTL				0x1bc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SOLID_COLOR				0x1bc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define WINDOW_XY_OFFSET			0x1bcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DRAW_LINE_POINT				0x1bd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SETUP_CNTL_PM4				0x1bd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DST_PITCH_OFFSET_C			0x1c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DP_GUI_MASTER_CNTL_C			0x1c84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SC_TOP_LEFT_C				0x1c88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SC_BOTTOM_RIGHT_C			0x1c8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLR_CMP_MASK_3D				0x1A28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MISC_3D_STATE_CNTL_REG			0x1CA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MC_SRC1_CNTL				0x19D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEX_CNTL				0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* CONSTANTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GUI_ACTIVE				0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ENGINE_IDLE				0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PLL_WR_EN				0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_PIN_CNTL				0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PPLL_CNTL				0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PPLL_REF_DIV				0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PPLL_DIV_0				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PPLL_DIV_1				0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PPLL_DIV_2				0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PPLL_DIV_3				0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define VCLK_ECP_CNTL				0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HTOTAL_CNTL				0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define X_MPLL_REF_FB_DIV			0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define XPLL_CNTL				0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define XDLL_CNTL				0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define XCLK_CNTL				0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MPLL_CNTL				0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MCLK_CNTL				0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AGP_PLL_CNTL				0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define FCP_CNTL				0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PLL_TEST_CNTL				0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define P2PLL_CNTL				0x002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define P2PLL_REF_DIV				0x002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define P2PLL_DIV_0				0x002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define POWER_MANAGEMENT			0x002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PPLL_RESET				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PPLL_ATOMIC_UPDATE_EN			0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PPLL_VGA_ATOMIC_UPDATE_EN		0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PPLL_REF_DIV_MASK			0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PPLL_FB3_DIV_MASK			0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PPLL_POST3_DIV_MASK			0x70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PPLL_ATOMIC_UPDATE_R			0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PPLL_ATOMIC_UPDATE_W			0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MEM_CFG_TYPE_MASK			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define XCLK_SRC_SEL_MASK			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define XPLL_FB_DIV_MASK			0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define X_MPLL_REF_DIV_MASK			0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* CRTC control values (CRTC_GEN_CNTL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CRTC_CSYNC_EN				0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CRTC2_DBL_SCAN_EN			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CRTC2_DISPLAY_DIS			0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CRTC2_FIFO_EXTSENSE			0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CRTC2_ICON_EN				0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CRTC2_CUR_EN				0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CRTC2_EN				0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CRTC2_DISP_REQ_EN_B			0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CRTC_PIX_WIDTH_MASK			0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CRTC_PIX_WIDTH_4BPP			0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CRTC_PIX_WIDTH_8BPP			0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CRTC_PIX_WIDTH_15BPP			0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CRTC_PIX_WIDTH_16BPP			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CRTC_PIX_WIDTH_24BPP			0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CRTC_PIX_WIDTH_32BPP			0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* DAC_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DAC_8BIT_EN				0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DAC_MASK				0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DAC_BLANKING				0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DAC_RANGE_CNTL				0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DAC_CLK_SEL				0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DAC_PALETTE_ACCESS_CNTL			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DAC_PALETTE2_SNOOP_EN			0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DAC_PDWN				0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* CRTC_EXT_CNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CRT_CRTC_ON				0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* GEN_RESET_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SOFT_RESET_GUI				0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SOFT_RESET_VCLK				0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SOFT_RESET_PCLK				0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SOFT_RESET_ECP				0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SOFT_RESET_DISPENG_XCLK			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* PC_GUI_CTLSTAT bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PC_BUSY_INIT				0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PC_BUSY_GUI				0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PC_BUSY_NGUI				0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define PC_BUSY					0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define BUS_MASTER_DIS				0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PM4_BUFFER_CNTL_NONPM4			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* DP_DATATYPE bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DST_8BPP				0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DST_15BPP				0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DST_16BPP				0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DST_24BPP				0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DST_32BPP				0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define BRUSH_SOLIDCOLOR			0x00000d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* DP_GUI_MASTER_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define	GMC_SRC_PITCH_OFFSET_DEFAULT		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define GMC_DST_PITCH_OFFSET_DEFAULT		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define GMC_SRC_CLIP_DEFAULT			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GMC_DST_CLIP_DEFAULT			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define GMC_BRUSH_SOLIDCOLOR			0x000000d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define GMC_SRC_DSTCOLOR			0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define GMC_BYTE_ORDER_MSB_TO_LSB		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define GMC_DP_SRC_RECT				0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define GMC_3D_FCN_EN_CLR			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define GMC_AUX_CLIP_CLEAR			0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GMC_DST_CLR_CMP_FCN_CLEAR		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define GMC_WRITE_MASK_SET			0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define GMC_DP_CONVERSION_TEMP_6500		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* DP_GUI_MASTER_CNTL ROP3 named constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define	ROP3_PATCOPY				0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ROP3_SRCCOPY				0x00cc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRC_DSTCOLOR				0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* DP_CNTL bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DST_X_RIGHT_TO_LEFT			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DST_X_LEFT_TO_RIGHT			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DST_Y_BOTTOM_TO_TOP			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DST_Y_TOP_TO_BOTTOM			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DST_X_MAJOR				0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DST_Y_MAJOR				0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DST_X_TILE				0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DST_Y_TILE				0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DST_LAST_PEL				0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DST_TRAIL_X_RIGHT_TO_LEFT		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DST_TRAIL_X_LEFT_TO_RIGHT		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DST_TRAP_FILL_RIGHT_TO_LEFT		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DST_TRAP_FILL_LEFT_TO_RIGHT		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DST_BRES_SIGN				0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DST_HOST_BIG_ENDIAN_EN			0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DST_POLYLINE_NONLAST			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DST_RASTER_STALL			0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define DST_POLY_EDGE				0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* DP_MIX bit constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DP_SRC_RECT				0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DP_SRC_HOST				0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DP_SRC_HOST_BYTEALIGN			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* LVDS_GEN_CNTL constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define LVDS_BL_MOD_LEVEL_MASK			0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define LVDS_BL_MOD_LEVEL_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define LVDS_BL_MOD_EN				0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define LVDS_DIGION				0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define LVDS_BLON				0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define LVDS_ON					0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define LVDS_DISPLAY_DIS			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define LVDS_PANEL_TYPE_2PIX_PER_CLK		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define LVDS_PANEL_24BITS_TFT			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define LVDS_FRAME_MOD_NO			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define LVDS_FRAME_MOD_2_LEVELS			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define LVDS_FRAME_MOD_4_LEVELS			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define LVDS_RST_FM				0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define LVDS_EN					0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* CRTC2_GEN_CNTL constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CRTC2_EN				0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* POWER_MANAGEMENT constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PWR_MGT_ON				0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PWR_MGT_MODE_MASK			0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PWR_MGT_MODE_PIN			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PWR_MGT_MODE_REGISTER			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PWR_MGT_MODE_TIMER			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PWR_MGT_MODE_PCI			0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PWR_MGT_AUTO_PWR_UP_EN			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PWR_MGT_ACTIVITY_PIN_ON			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PWR_MGT_STANDBY_POL			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PWR_MGT_SUSPEND_POL			0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PWR_MGT_SELF_REFRESH			0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PWR_MGT_ACTIVITY_PIN_EN			0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PWR_MGT_KEYBD_SNOOP			0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PWR_MGT_TRISTATE_MEM_EN			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PWR_MGT_SELW4MS				0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PWR_MGT_SLOWDOWN_MCLK			0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PMI_PMSCR_REG				0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* used by ATI bug fix for hardware ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define RAGE128_MPP_TB_CONFIG                   0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #endif				/* REG_RAGE128_H */