^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Header file for AT91/AT32 LCD Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Data structure and register user interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2007 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ATMEL_LCDC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ATMEL_LCDC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Way LCD wires are connected to the chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Some Atmel chips use BGR color mode (instead of standard RGB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * A swapped wiring onboard can bring to RGB mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ATMEL_LCDC_WIRING_BGR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ATMEL_LCDC_WIRING_RGB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* LCD Controller info data structure, stored in device platform_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct atmel_lcdfb_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int guard_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) bool lcdcon_is_backlight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bool lcdcon_pol_negative;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 default_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 lcd_wiring_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int default_lcdcon2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int default_dmacon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct fb_monspecs *default_monspecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct list_head pwr_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ATMEL_LCDC_DMABADDR1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ATMEL_LCDC_DMABADDR2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ATMEL_LCDC_DMAFRMPT1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ATMEL_LCDC_DMAFRMPT2 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ATMEL_LCDC_DMAFRMADD1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ATMEL_LCDC_DMAFRMADD2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ATMEL_LCDC_DMAFRMCFG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ATMEL_LCDC_BLENGTH_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ATMEL_LCDC_DMACON 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ATMEL_LCDC_DMAEN (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ATMEL_LCDC_DMARST (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ATMEL_LCDC_DMABUSY (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ATMEL_LCDC_DMAUPDT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ATMEL_LCDC_DMA2DEN (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ATMEL_LCDC_DMA2DCFG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ATMEL_LCDC_ADDRINC_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATMEL_LCDC_ADDRINC (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ATMEL_LCDC_PIXELOFF_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ATMEL_LCDC_PIXELOFF (0x1f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATMEL_LCDC_LCDCON1 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATMEL_LCDC_BYPASS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ATMEL_LCDC_CLKVAL_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ATMEL_LCDC_LINCNT (0x7ff << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ATMEL_LCDC_LCDCON2 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ATMEL_LCDC_DISTYPE (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ATMEL_LCDC_DISTYPE_TFT (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ATMEL_LCDC_SCANMOD (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ATMEL_LCDC_SCANMOD_DUAL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ATMEL_LCDC_IFWIDTH (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ATMEL_LCDC_IFWIDTH_4 (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ATMEL_LCDC_IFWIDTH_8 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ATMEL_LCDC_IFWIDTH_16 (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ATMEL_LCDC_PIXELSIZE (7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ATMEL_LCDC_PIXELSIZE_1 (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ATMEL_LCDC_PIXELSIZE_2 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ATMEL_LCDC_PIXELSIZE_4 (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ATMEL_LCDC_PIXELSIZE_8 (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ATMEL_LCDC_PIXELSIZE_16 (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ATMEL_LCDC_PIXELSIZE_24 (5 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ATMEL_LCDC_PIXELSIZE_32 (6 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ATMEL_LCDC_INVVD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ATMEL_LCDC_INVVD_NORMAL (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ATMEL_LCDC_INVVD_INVERTED (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ATMEL_LCDC_INVFRAME (1 << 9 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ATMEL_LCDC_INVLINE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ATMEL_LCDC_INVLINE_NORMAL (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ATMEL_LCDC_INVLINE_INVERTED (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ATMEL_LCDC_INVCLK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ATMEL_LCDC_INVCLK_NORMAL (0 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ATMEL_LCDC_INVCLK_INVERTED (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ATMEL_LCDC_INVDVAL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ATMEL_LCDC_CLKMOD (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ATMEL_LCDC_MEMOR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ATMEL_LCDC_MEMOR_BIG (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ATMEL_LCDC_TIM1 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ATMEL_LCDC_VFP (0xffU << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ATMEL_LCDC_VBP_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ATMEL_LCDC_VPW_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ATMEL_LCDC_VHDLY_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ATMEL_LCDC_TIM2 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ATMEL_LCDC_HBP (0xffU << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ATMEL_LCDC_HPW_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ATMEL_LCDC_HFP_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ATMEL_LCDC_LCDFRMCFG 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ATMEL_LCDC_LINEVAL (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ATMEL_LCDC_HOZVAL_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ATMEL_LCDC_FIFO 0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ATMEL_LCDC_FIFOTH (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ATMEL_LCDC_MVAL 0x0818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ATMEL_LCDC_DP1_2 0x081c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ATMEL_LCDC_DP4_7 0x0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ATMEL_LCDC_DP3_5 0x0824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ATMEL_LCDC_DP2_3 0x0828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ATMEL_LCDC_DP5_7 0x082c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ATMEL_LCDC_DP3_4 0x0830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ATMEL_LCDC_DP4_5 0x0834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ATMEL_LCDC_DP6_7 0x0838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ATMEL_LCDC_DP1_2_VAL (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ATMEL_LCDC_DP4_7_VAL (0xfffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ATMEL_LCDC_DP3_5_VAL (0xfffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ATMEL_LCDC_DP2_3_VAL (0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ATMEL_LCDC_DP5_7_VAL (0xfffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ATMEL_LCDC_DP3_4_VAL (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ATMEL_LCDC_DP4_5_VAL (0xfffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ATMEL_LCDC_DP6_7_VAL (0xfffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ATMEL_LCDC_PWRCON 0x083c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ATMEL_LCDC_PWR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ATMEL_LCDC_GUARDT_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ATMEL_LCDC_BUSY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ATMEL_LCDC_CONTRAST_CTR 0x0840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ATMEL_LCDC_PS (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ATMEL_LCDC_PS_DIV1 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ATMEL_LCDC_PS_DIV2 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ATMEL_LCDC_PS_DIV4 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ATMEL_LCDC_PS_DIV8 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ATMEL_LCDC_POL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ATMEL_LCDC_POL_NEGATIVE (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ATMEL_LCDC_POL_POSITIVE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ATMEL_LCDC_ENA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ATMEL_LCDC_ENA_PWMENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ATMEL_LCDC_CONTRAST_VAL 0x0844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ATMEL_LCDC_CVAL (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ATMEL_LCDC_IER 0x0848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ATMEL_LCDC_IDR 0x084c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ATMEL_LCDC_IMR 0x0850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ATMEL_LCDC_ISR 0x0854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ATMEL_LCDC_ICR 0x0858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ATMEL_LCDC_LNI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ATMEL_LCDC_LSTLNI (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ATMEL_LCDC_EOFI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ATMEL_LCDC_UFLWI (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ATMEL_LCDC_OWRI (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ATMEL_LCDC_MERI (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif /* __ATMEL_LCDC_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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