Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_HDSPM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_HDSPM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *   Copyright (C) 2003 Winfried Ritsch (IEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   based on hdsp.h from Thomas Charbonnel (thomas@undata.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *   This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *   it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *   the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *   This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *   GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *   You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *   along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #ifdef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Maximum channels is 64 even on 56Mode you have 64playbacks to matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HDSPM_MAX_CHANNELS      64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) enum hdspm_io_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	MADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	MADIface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	AIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	AES32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	RayDAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) enum hdspm_speed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	ds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	qs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* -------------------- IOCTL Peak/RMS Meters -------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct hdspm_peak_rms {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	__u32 input_peaks[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	__u32 playback_peaks[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	__u32 output_peaks[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	__u64 input_rms[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	__u64 playback_rms[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	__u64 output_rms[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	__u8 speed; /* enum {ss, ds, qs} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SNDRV_HDSPM_IOCTL_GET_PEAK_RMS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	_IOR('H', 0x42, struct hdspm_peak_rms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* ------------ CONFIG block IOCTL ---------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) struct hdspm_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned char pref_sync_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned char wordclock_sync_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned char madi_sync_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int system_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned int autosync_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned char system_clock_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned char clock_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned char autosync_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned char line_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned int passthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned int analog_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SNDRV_HDSPM_IOCTL_GET_CONFIG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	_IOR('H', 0x41, struct hdspm_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * If there's a TCO (TimeCode Option) board installed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * there are further options and status data available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * The hdspm_ltc structure contains the current SMPTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * timecode and some status information and can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * obtained via SNDRV_HDSPM_IOCTL_GET_LTC or in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * hdspm_status struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) enum hdspm_ltc_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	format_invalid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	fps_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	fps_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	fps_2997,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	fps_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) enum hdspm_ltc_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	frame_invalid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	drop_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	full_frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum hdspm_ltc_input_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ntsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	pal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	no_video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct hdspm_ltc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned int ltc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	enum hdspm_ltc_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	enum hdspm_ltc_frame frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	enum hdspm_ltc_input_format input_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SNDRV_HDSPM_IOCTL_GET_LTC _IOR('H', 0x46, struct hdspm_ltc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * The status data reflects the device's current state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * as determined by the card's configuration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * connection status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum hdspm_sync {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	hdspm_sync_no_lock = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	hdspm_sync_lock = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	hdspm_sync_sync = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum hdspm_madi_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	hdspm_input_optical = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	hdspm_input_coax = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum hdspm_madi_channel_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	hdspm_format_ch_64 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	hdspm_format_ch_56 = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum hdspm_madi_frame_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	hdspm_frame_48 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	hdspm_frame_96 = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum hdspm_syncsource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	syncsource_wc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	syncsource_madi = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	syncsource_tco = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	syncsource_sync = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	syncsource_none = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct hdspm_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	__u8 card_type; /* enum hdspm_io_type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	enum hdspm_syncsource autosync_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	__u64 card_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	__u32 master_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			__u8 sync_wc; /* enum hdspm_sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			__u8 sync_madi; /* enum hdspm_sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			__u8 sync_tco; /* enum hdspm_sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			__u8 sync_in; /* enum hdspm_sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			__u8 madi_input; /* enum hdspm_madi_input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			__u8 channel_format; /* enum hdspm_madi_channel_format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			__u8 frame_format; /* enum hdspm_madi_frame_format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		} madi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	} card_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SNDRV_HDSPM_IOCTL_GET_STATUS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	_IOR('H', 0x47, struct hdspm_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * Get information about the card and its add-ons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HDSPM_ADDON_TCO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct hdspm_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__u8 card_type; /* enum hdspm_io_type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	char cardname[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	unsigned int serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	unsigned short firmware_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int addons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SNDRV_HDSPM_IOCTL_GET_VERSION _IOR('H', 0x48, struct hdspm_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* ------------- get Matrix Mixer IOCTL --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* MADI mixer: 64inputs+64playback in 64outputs = 8192 => *4Byte =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * 32768 Bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* organisation is 64 channelfader in a continuous memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* equivalent to hardware definition, maybe for future feature of mmap of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* each of 64 outputs has 64 infader and 64 outfader:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)    Ins to Outs mixer[out].in[in], Outstreams to Outs mixer[out].pb[pb] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HDSPM_MIXER_CHANNELS HDSPM_MAX_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct hdspm_channelfader {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned int in[HDSPM_MIXER_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned int pb[HDSPM_MIXER_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct hdspm_mixer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct hdspm_channelfader ch[HDSPM_MIXER_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct hdspm_mixer_ioctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct hdspm_mixer *mixer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* use indirect access due to the limit of ioctl bit size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SNDRV_HDSPM_IOCTL_GET_MIXER _IOR('H', 0x44, struct hdspm_mixer_ioctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif