^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Creative Labs, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Definitions for EMU10K1 (SB Live!) chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef _UAPI__SOUND_EMU10K1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define _UAPI__SOUND_EMU10K1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * ---- FX8010 ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EMU10K1_CARD_CREATIVE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EMU10K1_CARD_EMUAPS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EMU10K1_FX8010_PCM_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Following definition is copied from linux/types.h to support compiling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * this header file in userspace since they are not generally available for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * uapi headers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define __EMU10K1_DECLARE_BITMAP(name,bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* instruction set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define iACC3 0x06 /* R = A + X + Y ; saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define iANDXOR 0x08 /* R = (A & X) ^ Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* GPRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define C_00000000 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define C_00000001 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define C_00000002 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define C_00000003 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define C_00000004 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define C_00000008 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define C_00000010 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define C_00000020 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define C_00000100 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define C_00010000 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define C_00080000 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define C_10000000 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define C_20000000 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define C_40000000 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define C_80000000 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define C_7fffffff 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define C_ffffffff 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define C_fffffffe 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define C_c0000000 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define C_4f1bbcdc 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define C_5a7ef9db 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define C_00100000 0x55 /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GPR_ACCU 0x56 /* ACCUM, accumulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GPR_COND 0x57 /* CCR, condition register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPR_NOISE0 0x58 /* noise source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPR_NOISE1 0x59 /* noise source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GPR_IRQ 0x5a /* IRQ register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define A_GPR(x) (A_FXGPREGBASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* cc_reg constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CC_REG_NORMALIZED C_00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CC_REG_BORROW C_00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CC_REG_MINUS C_00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CC_REG_ZERO C_00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CC_REG_SATURATE C_00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CC_REG_NONZERO C_00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* FX buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FXBUS_PCM_LEFT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FXBUS_PCM_RIGHT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FXBUS_PCM_LEFT_REAR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FXBUS_PCM_RIGHT_REAR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FXBUS_MIDI_LEFT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FXBUS_MIDI_RIGHT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FXBUS_PCM_CENTER 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FXBUS_PCM_LFE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FXBUS_PCM_LEFT_FRONT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FXBUS_PCM_RIGHT_FRONT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FXBUS_MIDI_REVERB 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FXBUS_MIDI_CHORUS 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FXBUS_PCM_LEFT_SIDE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FXBUS_PCM_RIGHT_SIDE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FXBUS_PT_LEFT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FXBUS_PT_RIGHT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EXTOUT_ACENTER 0x11 /* Analog Center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EXTOUT_ALFE 0x12 /* Analog LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Audigy Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define A_EXTIN_LINE2_R 0x09 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define A_EXTIN_ADC_R 0x0b /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define A_EXTIN_AUX2_R 0x0d /* - right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Audigiy Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define A_EXTOUT_FRONT_R 0x01 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define A_EXTOUT_CENTER 0x02 /* digital front center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define A_EXTOUT_LFE 0x03 /* digital front lfe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define A_EXTOUT_REAR_R 0x07 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define A_EXTOUT_AFRONT_R 0x09 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define A_EXTOUT_ACENTER 0x0a /* analog center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define A_EXTOUT_ALFE 0x0b /* analog LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define A_EXTOUT_AREAR_R 0x0f /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define A_EXTOUT_AC97_R 0x11 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Audigy constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define A_C_00000000 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define A_C_00000001 0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define A_C_00000002 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define A_C_00000003 0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define A_C_00000004 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define A_C_00000008 0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define A_C_00000010 0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define A_C_00000020 0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define A_C_00000100 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define A_C_00010000 0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define A_C_00000800 0xca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define A_C_10000000 0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define A_C_20000000 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define A_C_40000000 0xcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define A_C_80000000 0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define A_C_7fffffff 0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define A_C_ffffffff 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define A_C_fffffffe 0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define A_C_c0000000 0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define A_C_4f1bbcdc 0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define A_C_5a7ef9db 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define A_C_00100000 0xd5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define A_GPR_COND 0xd7 /* CCR, condition register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define A_GPR_NOISE0 0xd8 /* noise source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define A_GPR_NOISE1 0xd9 /* noise source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define A_GPR_IRQ 0xda /* IRQ register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* definitions for debug register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* tank memory address line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifndef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_emu10k1_fx8010_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int internal_tram_size; /* in samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int external_tram_size; /* in samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) char fxbus_names[16][32]; /* names of FXBUSes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) char extin_names[16][32]; /* names of external inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) char extout_names[32][32]; /* names of external outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int gpr_controls; /* count of GPR controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define EMU10K1_GPR_TRANSLATION_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define EMU10K1_GPR_TRANSLATION_TABLE100 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define EMU10K1_GPR_TRANSLATION_BASS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define EMU10K1_GPR_TRANSLATION_TREBLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define EMU10K1_GPR_TRANSLATION_ONOFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) enum emu10k1_ctl_elem_iface {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) EMU10K1_CTL_ELEM_IFACE_MIXER = 2, /* virtual mixer device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) EMU10K1_CTL_ELEM_IFACE_PCM = 3, /* PCM device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct emu10k1_ctl_elem_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int pad; /* don't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int iface; /* interface identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int device; /* device/client number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int subdevice; /* subdevice (substream) number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned char name[44]; /* ASCII name of item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int index; /* index of item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct snd_emu10k1_fx8010_control_gpr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct emu10k1_ctl_elem_id id; /* full control ID definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int vcount; /* visible count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int count; /* count of GPR (1..16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned short gpr[32]; /* GPR number(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int value[32]; /* initial values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int min; /* minimum range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int max; /* maximum range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) const unsigned int *tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* old ABI without TLV support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct snd_emu10k1_fx8010_control_old_gpr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct emu10k1_ctl_elem_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int vcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned short gpr[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int value[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int translation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct snd_emu10k1_fx8010_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) char name[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) __u32 *gpr_map; /* initializers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int gpr_del_control_count; /* count of GPR controls to remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct emu10k1_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int gpr_list_control_count; /* count of GPR controls to list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int gpr_list_control_total; /* total count of GPR controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __u32 *tram_data_map; /* data initializers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) __u32 *tram_addr_map; /* map initializers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __u32 *code; /* one instruction - 64 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct snd_emu10k1_fx8010_tram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int address; /* 31.bit == 1 -> external TRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int size; /* size in samples (4 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int *samples; /* pointer to samples (20-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* NULL->clear memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct snd_emu10k1_fx8010_pcm_rec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int substream; /* substream number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int res1; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int channels; /* 16-bit channels count, zero = remove this substream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int buffer_size; /* count of buffered samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned char pad; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned char etram[32]; /* external TRAM address & data (one per channel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int res2; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif /* _UAPI__SOUND_EMU10K1_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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