^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Advanced Linux Sound Architecture - ALSA - Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1994-2003 by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Abramo Bagnara <abramo@alsa-project.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef _UAPI__SOUND_ASOUND_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define _UAPI__SOUND_ASOUND_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #if defined(__KERNEL__) || defined(__linux__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <endian.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sys/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <stdlib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * protocol version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Digital audio interface *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct snd_aes_iec958 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned char status[24]; /* AES/IEC958 channel status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned char subcode[147]; /* AES/IEC958 subcode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned char pad; /* nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned char dig_subframe[4]; /* AES/IEC958 subframe bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * CEA-861 Audio InfoFrame. Used in HDMI and DisplayPort *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct snd_cea_861_aud_if {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned char db1_ct_cc; /* coding type and channel count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned char db2_sf_ss; /* sample frequency and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned char db3; /* not used, all zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned char db4_ca; /* channel allocation code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned char db5_dminh_lsv; /* downmix inhibit & level-shit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Section for driver hardware dependent interface - /dev/snd/hw? *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SNDRV_HWDEP_IFACE_OPL2 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SNDRV_HWDEP_IFACE_OPL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SNDRV_HWDEP_IFACE_OPL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SNDRV_HWDEP_IFACE_SB16CSP, /* Creative Signal Processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SNDRV_HWDEP_IFACE_EMU10K1, /* FX8010 processor in EMU10K1 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SNDRV_HWDEP_IFACE_YSS225, /* Yamaha FX processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SNDRV_HWDEP_IFACE_ICS2115, /* Wavetable synth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SNDRV_HWDEP_IFACE_SSCAPE, /* Ensoniq SoundScape ISA card (MC68EC000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SNDRV_HWDEP_IFACE_VX, /* Digigram VX cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SNDRV_HWDEP_IFACE_MIXART, /* Digigram miXart cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SNDRV_HWDEP_IFACE_USX2Y, /* Tascam US122, US224 & US428 usb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SNDRV_HWDEP_IFACE_EMUX_WAVETABLE, /* EmuX wavetable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SNDRV_HWDEP_IFACE_BLUETOOTH, /* Bluetooth audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SNDRV_HWDEP_IFACE_USX2Y_PCM, /* Tascam US122, US224 & US428 rawusb pcm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SNDRV_HWDEP_IFACE_PCXHR, /* Digigram PCXHR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SNDRV_HWDEP_IFACE_SB_RC, /* SB Extigy/Audigy2NX remote control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SNDRV_HWDEP_IFACE_HDA, /* HD-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SNDRV_HWDEP_IFACE_USB_STREAM, /* direct access to usb stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SNDRV_HWDEP_IFACE_FW_DICE, /* TC DICE FireWire device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SNDRV_HWDEP_IFACE_FW_FIREWORKS, /* Echo Audio Fireworks based device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SNDRV_HWDEP_IFACE_FW_BEBOB, /* BridgeCo BeBoB based device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SNDRV_HWDEP_IFACE_FW_OXFW, /* Oxford OXFW970/971 based device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SNDRV_HWDEP_IFACE_FW_DIGI00X, /* Digidesign Digi 002/003 family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SNDRV_HWDEP_IFACE_FW_TASCAM, /* TASCAM FireWire series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SNDRV_HWDEP_IFACE_LINE6, /* Line6 USB processors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SNDRV_HWDEP_IFACE_FW_MOTU, /* MOTU FireWire series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SNDRV_HWDEP_IFACE_FW_FIREFACE, /* RME Fireface series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Don't forget to change the following: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_FIREFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct snd_hwdep_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int device; /* WR: device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int card; /* R: card number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned char id[64]; /* ID (user selectable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned char name[80]; /* hwdep name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int iface; /* hwdep interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned char reserved[64]; /* reserved for future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* generic DSP loader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct snd_hwdep_dsp_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int version; /* R: driver-specific version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned char id[32]; /* R: driver-specific ID string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int num_dsps; /* R: number of DSP images to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int dsp_loaded; /* R: bit flags indicating the loaded DSPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int chip_ready; /* R: 1 = initialization finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned char reserved[16]; /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct snd_hwdep_dsp_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int index; /* W: DSP index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char name[64]; /* W: ID (e.g. file name) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned char __user *image; /* W: binary image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) size_t length; /* W: size of image in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long driver_data; /* W: driver-specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Digital Audio (PCM) interface - /dev/snd/pcm?? *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) typedef unsigned long snd_pcm_uframes_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) typedef signed long snd_pcm_sframes_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SNDRV_PCM_CLASS_GENERIC = 0, /* standard mono or stereo device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SNDRV_PCM_CLASS_MULTI, /* multichannel device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SNDRV_PCM_CLASS_MODEM, /* software modem class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SNDRV_PCM_CLASS_DIGITIZER, /* digitizer class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Don't forget to change the following: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0, /* mono or stereo subdevices are mixed together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SNDRV_PCM_SUBCLASS_MULTI_MIX, /* multichannel subdevices are mixed together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Don't forget to change the following: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SNDRV_PCM_STREAM_PLAYBACK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) typedef int __bitwise snd_pcm_access_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0) /* interleaved mmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1) /* noninterleaved mmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2) /* complex mmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3) /* readi/writei */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4) /* readn/writen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) typedef int __bitwise snd_pcm_format_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6) /* low three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7) /* low three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8) /* low three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9) /* low three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14) /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15) /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16) /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17) /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18) /* IEC-958 subframe, Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19) /* IEC-958 subframe, Big Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SNDRV_PCM_FORMAT_S20_LE ((__force snd_pcm_format_t) 25) /* in four bytes, LSB justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SNDRV_PCM_FORMAT_S20_BE ((__force snd_pcm_format_t) 26) /* in four bytes, LSB justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SNDRV_PCM_FORMAT_U20_LE ((__force snd_pcm_format_t) 27) /* in four bytes, LSB justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SNDRV_PCM_FORMAT_U20_BE ((__force snd_pcm_format_t) 28) /* in four bytes, LSB justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* gap in the numbering for a future standard linear format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43) /* in three bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SNDRV_PCM_FORMAT_G723_24 ((__force snd_pcm_format_t) 44) /* 8 samples in 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45) /* 1 sample in 1 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46) /* 8 Samples in 5 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47) /* 1 sample in 1 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48) /* DSD, 1-byte samples DSD (x8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49) /* DSD, 2-byte samples DSD (x16), little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SNDRV_PCM_FORMAT_DSD_U32_LE ((__force snd_pcm_format_t) 50) /* DSD, 4-byte samples DSD (x32), little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SNDRV_PCM_FORMAT_DSD_U16_BE ((__force snd_pcm_format_t) 51) /* DSD, 2-byte samples DSD (x16), big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SNDRV_PCM_FORMAT_DSD_U32_BE ((__force snd_pcm_format_t) 52) /* DSD, 4-byte samples DSD (x32), big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U32_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SNDRV_PCM_FORMAT_FIRST SNDRV_PCM_FORMAT_S8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #ifdef SNDRV_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef SNDRV_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) typedef int __bitwise snd_pcm_subformat_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SNDRV_PCM_INFO_MMAP 0x00000001 /* hardware supports mmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SNDRV_PCM_INFO_MMAP_VALID 0x00000002 /* period data are valid during transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SNDRV_PCM_INFO_DOUBLE 0x00000004 /* Double buffering needed for PCM start/stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SNDRV_PCM_INFO_BATCH 0x00000010 /* double buffering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SNDRV_PCM_INFO_SYNC_APPLPTR 0x00000020 /* need the explicit sync of appl_ptr update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SNDRV_PCM_INFO_INTERLEAVED 0x00000100 /* channels are interleaved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200 /* channels are not interleaved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SNDRV_PCM_INFO_COMPLEX 0x00000400 /* complex frame organization (mmap only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000 /* hardware transfer block of samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SNDRV_PCM_INFO_OVERRANGE 0x00020000 /* hardware supports ADC (capture) overrange detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SNDRV_PCM_INFO_RESUME 0x00040000 /* hardware supports stream resume after suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SNDRV_PCM_INFO_PAUSE 0x00080000 /* pause ioctl is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000 /* only half duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000 /* playback and capture stream are somewhat correlated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SNDRV_PCM_INFO_SYNC_START 0x00400000 /* pcm support some kind of sync go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000 /* period wakeup can be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000 /* (Deprecated)has audio wall clock for audio/system time sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SNDRV_PCM_INFO_HAS_LINK_ATIME 0x01000000 /* report hardware link audio time, reset on startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SNDRV_PCM_INFO_HAS_LINK_ABSOLUTE_ATIME 0x02000000 /* report absolute hardware link audio time, not reset on startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000 /* report estimated link audio time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000 /* report synchronized audio/system time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000 /* internal kernel flag - trigger in drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 /* internal kernel flag - FIFO size is in frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #if (__BITS_PER_LONG == 32 && defined(__USE_TIME_BITS64)) || defined __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define __SND_STRUCT_TIME64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) typedef int __bitwise snd_pcm_state_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0) /* stream is open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1) /* stream has a setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2) /* stream is ready to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3) /* stream is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4) /* stream reached an xrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5) /* stream is draining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6) /* stream is paused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7) /* hardware is suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8) /* hardware is disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SNDRV_PCM_MMAP_OFFSET_STATUS_OLD = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SNDRV_PCM_MMAP_OFFSET_CONTROL_OLD = 0x81000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SNDRV_PCM_MMAP_OFFSET_STATUS_NEW = 0x82000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SNDRV_PCM_MMAP_OFFSET_CONTROL_NEW = 0x83000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef __SND_STRUCT_TIME64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SNDRV_PCM_MMAP_OFFSET_STATUS = SNDRV_PCM_MMAP_OFFSET_STATUS_NEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SNDRV_PCM_MMAP_OFFSET_CONTROL = SNDRV_PCM_MMAP_OFFSET_CONTROL_NEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SNDRV_PCM_MMAP_OFFSET_STATUS = SNDRV_PCM_MMAP_OFFSET_STATUS_OLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SNDRV_PCM_MMAP_OFFSET_CONTROL = SNDRV_PCM_MMAP_OFFSET_CONTROL_OLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) union snd_pcm_sync_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned char id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned short id16[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int id32[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct snd_pcm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int device; /* RO/WR (control): device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int subdevice; /* RO/WR (control): subdevice number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int stream; /* RO/WR (control): stream direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int card; /* R: card number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned char id[64]; /* ID (user selectable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned char name[80]; /* name of this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned char subname[32]; /* subdevice name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int dev_class; /* SNDRV_PCM_CLASS_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int dev_subclass; /* SNDRV_PCM_SUBCLASS_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int subdevices_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int subdevices_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) union snd_pcm_sync_id sync; /* hardware synchronization ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned char reserved[64]; /* reserved for future... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) typedef int snd_pcm_hw_param_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SNDRV_PCM_HW_PARAM_ACCESS 0 /* Access type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SNDRV_PCM_HW_PARAM_FORMAT 1 /* Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SNDRV_PCM_HW_PARAM_SUBFORMAT 2 /* Subformat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8 /* Bits per sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SNDRV_PCM_HW_PARAM_FRAME_BITS 9 /* Bits per frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SNDRV_PCM_HW_PARAM_CHANNELS 10 /* Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SNDRV_PCM_HW_PARAM_RATE 11 /* Approx rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12 /* Approx distance between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * interrupts in us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13 /* Approx frames between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14 /* Approx bytes between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SNDRV_PCM_HW_PARAM_PERIODS 15 /* Approx interrupts per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16 /* Approx duration of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * in us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17 /* Size of buffer in frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18 /* Size of buffer in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SNDRV_PCM_HW_PARAM_TICK_TIME 19 /* Approx tick duration in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0) /* avoid rate resampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1) /* export buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2) /* disable period wakeups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct snd_interval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int openmin:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) openmax:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) integer:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) empty:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SNDRV_MASK_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct snd_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __u32 bits[(SNDRV_MASK_MAX+31)/32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct snd_pcm_hw_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct snd_mask mres[5]; /* reserved masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct snd_interval ires[9]; /* reserved intervals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int rmask; /* W: requested masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned int cmask; /* R: changed masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int info; /* R: Info flags for returned setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int msbits; /* R: used most significant bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int rate_num; /* R: rate numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int rate_den; /* R: rate denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) snd_pcm_uframes_t fifo_size; /* R: chip FIFO size in frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned char reserved[64]; /* reserved for future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SNDRV_PCM_TSTAMP_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) SNDRV_PCM_TSTAMP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct snd_pcm_sw_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int tstamp_mode; /* timestamp mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int period_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int sleep_min; /* min ticks to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) snd_pcm_uframes_t avail_min; /* min avail frames for wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) snd_pcm_uframes_t xfer_align; /* obsolete: xfer size need to be a multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) snd_pcm_uframes_t start_threshold; /* min hw_avail frames for automatic start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snd_pcm_uframes_t stop_threshold; /* min avail frames for automatic stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) snd_pcm_uframes_t silence_threshold; /* min distance from noise for silence filling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) snd_pcm_uframes_t silence_size; /* silence block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) snd_pcm_uframes_t boundary; /* pointers wrap point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int proto; /* protocol version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int tstamp_type; /* timestamp type (req. proto >= 2.0.12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned char reserved[56]; /* reserved for future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct snd_pcm_channel_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) __kernel_off_t offset; /* mmap offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int first; /* offset to first sample in bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int step; /* samples distance in bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * first definition for backwards compatibility only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * maps to wallclock/link time for HDAudio playback and DEFAULT/DMA time for everything else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* timestamp definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1, /* DMA time, reported as per hw_ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2, /* link time reported by sample or wallclock counter, reset on startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3, /* link time reported by sample or wallclock counter, not reset on startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4, /* link time estimated indirectly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5, /* link time synchronized with system time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #ifndef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* explicit padding avoids incompatibility between i386 and x86-64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) typedef struct { unsigned char pad[sizeof(time_t) - sizeof(int)]; } __time_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct snd_pcm_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) snd_pcm_state_t state; /* stream state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) __time_pad pad1; /* align to timespec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct timespec trigger_tstamp; /* time when stream was started/stopped/paused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct timespec tstamp; /* reference timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) snd_pcm_uframes_t appl_ptr; /* appl ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) snd_pcm_uframes_t hw_ptr; /* hw ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) snd_pcm_sframes_t delay; /* current delay in frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) snd_pcm_uframes_t avail; /* number of frames available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) snd_pcm_uframes_t avail_max; /* max frames available on hw since last status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) snd_pcm_uframes_t overrange; /* count of ADC (capture) overrange detections from last status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_pcm_state_t suspended_state; /* suspended stream state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __u32 audio_tstamp_data; /* needed for 64-bit alignment, used for configs/report to/from userspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct timespec audio_tstamp; /* sample counter, wall clock, PHC or on-demand sync'ed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct timespec driver_tstamp; /* useful in case reference system tstamp is reported with delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned char reserved[52-2*sizeof(struct timespec)]; /* must be filled with zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * For mmap operations, we need the 64-bit layout, both for compat mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * and for y2038 compatibility. For 64-bit applications, the two definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * are identical, so we keep the traditional version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #ifdef __SND_STRUCT_TIME64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define __snd_pcm_mmap_status64 snd_pcm_mmap_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define __snd_pcm_mmap_control64 snd_pcm_mmap_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define __snd_pcm_sync_ptr64 snd_pcm_sync_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define __snd_timespec64 __kernel_timespec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define __snd_timespec64 timespec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct __snd_timespec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) __s32 tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) __s32 tv_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define __snd_pcm_mmap_status snd_pcm_mmap_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define __snd_pcm_mmap_control snd_pcm_mmap_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define __snd_pcm_sync_ptr snd_pcm_sync_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define __snd_timespec timespec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct __snd_timespec64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __s64 tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __s64 tv_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct __snd_pcm_mmap_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) snd_pcm_state_t state; /* RO: state - SNDRV_PCM_STATE_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int pad1; /* Needed for 64 bit alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct __snd_timespec tstamp; /* Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) snd_pcm_state_t suspended_state; /* RO: suspended stream state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct __snd_timespec audio_tstamp; /* from sample counter or wall clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct __snd_pcm_mmap_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0) /* execute hwsync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SNDRV_PCM_SYNC_PTR_APPL (1<<1) /* get appl_ptr from driver (r/w op) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) /* get avail_min from driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct __snd_pcm_sync_ptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct __snd_pcm_mmap_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned char reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct __snd_pcm_mmap_control control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned char reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) } c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #if defined(__BYTE_ORDER) ? __BYTE_ORDER == __BIG_ENDIAN : defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) typedef char __pad_before_uframe[sizeof(__u64) - sizeof(snd_pcm_uframes_t)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) typedef char __pad_after_uframe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #if defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) typedef char __pad_before_uframe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) typedef char __pad_after_uframe[sizeof(__u64) - sizeof(snd_pcm_uframes_t)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct __snd_pcm_mmap_status64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) snd_pcm_state_t state; /* RO: state - SNDRV_PCM_STATE_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __u32 pad1; /* Needed for 64 bit alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __pad_before_uframe __pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) __pad_after_uframe __pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct __snd_timespec64 tstamp; /* Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) snd_pcm_state_t suspended_state;/* RO: suspended stream state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __u32 pad3; /* Needed for 64 bit alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct __snd_timespec64 audio_tstamp; /* sample counter or wall clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct __snd_pcm_mmap_control64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) __pad_before_uframe __pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __pad_before_uframe __pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __pad_before_uframe __pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __pad_after_uframe __pad4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct __snd_pcm_sync_ptr64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __u32 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct __snd_pcm_mmap_status64 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned char reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct __snd_pcm_mmap_control64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned char reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct snd_xferi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) snd_pcm_sframes_t result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void __user *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) snd_pcm_uframes_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct snd_xfern {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) snd_pcm_sframes_t result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) void __user * __user *bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) snd_pcm_uframes_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0, /* gettimeofday equivalent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, /* posix_clock_monotonic equivalent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, /* monotonic_raw (no NTP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* channel positions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SNDRV_CHMAP_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SNDRV_CHMAP_NA, /* N/A, silent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) SNDRV_CHMAP_MONO, /* mono stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* this follows the alsa-lib mixer channel value + 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SNDRV_CHMAP_FL, /* front left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SNDRV_CHMAP_FR, /* front right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SNDRV_CHMAP_RL, /* rear left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) SNDRV_CHMAP_RR, /* rear right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SNDRV_CHMAP_FC, /* front center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) SNDRV_CHMAP_LFE, /* LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SNDRV_CHMAP_SL, /* side left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SNDRV_CHMAP_SR, /* side right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SNDRV_CHMAP_RC, /* rear center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* new definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SNDRV_CHMAP_FLC, /* front left center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SNDRV_CHMAP_FRC, /* front right center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) SNDRV_CHMAP_RLC, /* rear left center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SNDRV_CHMAP_RRC, /* rear right center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) SNDRV_CHMAP_FLW, /* front left wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SNDRV_CHMAP_FRW, /* front right wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SNDRV_CHMAP_FLH, /* front left high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SNDRV_CHMAP_FCH, /* front center high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) SNDRV_CHMAP_FRH, /* front right high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SNDRV_CHMAP_TC, /* top center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SNDRV_CHMAP_TFL, /* top front left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SNDRV_CHMAP_TFR, /* top front right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SNDRV_CHMAP_TFC, /* top front center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SNDRV_CHMAP_TRL, /* top rear left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) SNDRV_CHMAP_TRR, /* top rear right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SNDRV_CHMAP_TRC, /* top rear center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* new definitions for UAC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SNDRV_CHMAP_TFLC, /* top front left center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SNDRV_CHMAP_TFRC, /* top front right center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SNDRV_CHMAP_TSL, /* top side left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SNDRV_CHMAP_TSR, /* top side right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SNDRV_CHMAP_LLFE, /* left LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SNDRV_CHMAP_RLFE, /* right LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SNDRV_CHMAP_BC, /* bottom center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SNDRV_CHMAP_BLC, /* bottom left center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SNDRV_CHMAP_BRC, /* bottom right center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SNDRV_CHMAP_POSITION_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define SNDRV_PCM_IOCTL_USER_PVERSION _IOW('A', 0x04, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define __SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct __snd_pcm_sync_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define __SNDRV_PCM_IOCTL_SYNC_PTR64 _IOWR('A', 0x23, struct __snd_pcm_sync_ptr64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SNDRV_PCM_IOCTL_START _IO('A', 0x42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * MIDI v1.0 interface *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Raw MIDI section - /dev/snd/midi??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SNDRV_RAWMIDI_STREAM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct snd_rawmidi_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned int device; /* RO/WR (control): device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unsigned int subdevice; /* RO/WR (control): subdevice number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int stream; /* WR: stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int card; /* R: card number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned int flags; /* SNDRV_RAWMIDI_INFO_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) unsigned char id[64]; /* ID (user selectable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned char name[80]; /* name of device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned char subname[32]; /* name of active or selected subdevice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned int subdevices_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unsigned int subdevices_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned char reserved[64]; /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct snd_rawmidi_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) size_t buffer_size; /* queue size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) size_t avail_min; /* minimum avail bytes for wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned int no_active_sensing: 1; /* do not send active sensing byte in close() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned char reserved[16]; /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #ifndef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct snd_rawmidi_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) __time_pad pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct timespec tstamp; /* Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) size_t avail; /* available bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) size_t xruns; /* count of overruns since last status (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) unsigned char reserved[16]; /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Timer section - /dev/snd/timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) SNDRV_TIMER_CLASS_NONE = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SNDRV_TIMER_CLASS_SLAVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) SNDRV_TIMER_CLASS_GLOBAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) SNDRV_TIMER_CLASS_CARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) SNDRV_TIMER_CLASS_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* slave timer classes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) SNDRV_TIMER_SCLASS_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) SNDRV_TIMER_SCLASS_APPLICATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SNDRV_TIMER_SCLASS_SEQUENCER, /* alias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) SNDRV_TIMER_SCLASS_OSS_SEQUENCER, /* alias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* global timers (device member) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define SNDRV_TIMER_GLOBAL_SYSTEM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define SNDRV_TIMER_GLOBAL_RTC 1 /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define SNDRV_TIMER_GLOBAL_HPET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SNDRV_TIMER_GLOBAL_HRTIMER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SNDRV_TIMER_FLG_SLAVE (1<<0) /* cannot be controlled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct snd_timer_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int dev_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int dev_sclass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct snd_timer_ginfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct snd_timer_id tid; /* requested timer ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int card; /* card number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned char id[64]; /* timer identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned char name[80]; /* timer name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned long reserved0; /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned long resolution; /* average period resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned long resolution_min; /* minimal period resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) unsigned long resolution_max; /* maximal period resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned int clients; /* active timer clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned char reserved[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct snd_timer_gparams {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct snd_timer_id tid; /* requested timer ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned long period_num; /* requested precise period duration (in seconds) - numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned long period_den; /* requested precise period duration (in seconds) - denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unsigned char reserved[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct snd_timer_gstatus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct snd_timer_id tid; /* requested timer ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned long resolution; /* current period resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) unsigned long resolution_num; /* precise current period resolution (in seconds) - numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) unsigned long resolution_den; /* precise current period resolution (in seconds) - denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned char reserved[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct snd_timer_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct snd_timer_id id; /* bind to timer ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) unsigned char reserved[32]; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct snd_timer_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int card; /* card number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned char id[64]; /* timer identificator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned char name[80]; /* timer name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) unsigned long reserved0; /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) unsigned long resolution; /* average period resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) unsigned char reserved[64]; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define SNDRV_TIMER_PSFLG_AUTO (1<<0) /* auto start, otherwise one-shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1) /* exclusive use, precise start/stop/pause/continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2) /* write early event to the poll queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct snd_timer_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unsigned int flags; /* flags - SNDRV_TIMER_PSFLG_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned int ticks; /* requested resolution in ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) unsigned int queue_size; /* total size of queue (32-1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unsigned int reserved0; /* reserved, was: failure locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned int filter; /* event filter (bitmask of SNDRV_TIMER_EVENT_*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) unsigned char reserved[60]; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #ifndef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct snd_timer_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct timespec tstamp; /* Timestamp - last update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) unsigned int resolution; /* current period resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) unsigned int lost; /* counter of master tick lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned int overrun; /* count of read queue overruns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int queue; /* used queue size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned char reserved[64]; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define SNDRV_TIMER_IOCTL_TREAD_OLD _IOW('T', 0x02, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* The following four ioctls are changed since 1.0.9 due to confliction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define SNDRV_TIMER_IOCTL_TREAD64 _IOW('T', 0xa4, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #if __BITS_PER_LONG == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define SNDRV_TIMER_IOCTL_TREAD SNDRV_TIMER_IOCTL_TREAD_OLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define SNDRV_TIMER_IOCTL_TREAD ((sizeof(__kernel_long_t) >= sizeof(time_t)) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) SNDRV_TIMER_IOCTL_TREAD_OLD : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SNDRV_TIMER_IOCTL_TREAD64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct snd_timer_read {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) unsigned int resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned int ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) SNDRV_TIMER_EVENT_RESOLUTION = 0, /* val = resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) SNDRV_TIMER_EVENT_TICK, /* val = ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SNDRV_TIMER_EVENT_START, /* val = resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) SNDRV_TIMER_EVENT_STOP, /* val = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SNDRV_TIMER_EVENT_CONTINUE, /* val = resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) SNDRV_TIMER_EVENT_PAUSE, /* val = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) SNDRV_TIMER_EVENT_EARLY, /* val = 0, early event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) SNDRV_TIMER_EVENT_SUSPEND, /* val = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SNDRV_TIMER_EVENT_RESUME, /* val = resolution in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* master timer events for slave timer instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #ifndef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct snd_timer_tread {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) __time_pad pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct timespec tstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) __time_pad pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * Section for driver control interface - /dev/snd/control? *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct snd_ctl_card_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int card; /* card number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int pad; /* reserved for future (was type) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned char id[16]; /* ID of card (user selectable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) unsigned char driver[16]; /* Driver name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned char name[32]; /* Short name of soundcard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) unsigned char longname[80]; /* name + info text about soundcard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned char reserved_[16]; /* reserved for future (was ID of mixer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) unsigned char mixername[80]; /* visual mixer identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) unsigned char components[128]; /* card components / fine identification, delimited with one space (AC97 etc..) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) typedef int __bitwise snd_ctl_elem_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0) /* invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1) /* boolean type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2) /* integer type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3) /* enumerated type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4) /* byte array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5) /* IEC958 (S/PDIF) setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6) /* 64-bit integer type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) typedef int __bitwise snd_ctl_elem_iface_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0) /* global control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1) /* hardware dependent device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2) /* virtual mixer device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3) /* PCM device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4) /* RawMidi device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5) /* timer device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6) /* sequencer client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define SNDRV_CTL_ELEM_ACCESS_READ (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) /* control value may be changed without a notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) // (1 << 3) is unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4) /* TLV read is possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5) /* TLV write is possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6) /* TLV command is possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8) /* control does actually nothing, but may be updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9) /* write lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10) /* write lock owner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28) /* kernel use a TLV callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define SNDRV_CTL_ELEM_ACCESS_USER (1<<29) /* user space element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* bits 30 and 31 are obsoleted (for indirect access) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* for further details see the ACPI and PCI power management specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define SNDRV_CTL_POWER_D0 0x0000 /* full On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define SNDRV_CTL_POWER_D1 0x0100 /* partial On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define SNDRV_CTL_POWER_D2 0x0200 /* partial On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define SNDRV_CTL_POWER_D3 0x0300 /* Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000) /* Off, with power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001) /* Off, without power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct snd_ctl_elem_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int numid; /* numeric identifier, zero = invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) snd_ctl_elem_iface_t iface; /* interface identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) unsigned int device; /* device/client number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned int subdevice; /* subdevice (substream) number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) unsigned char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; /* ASCII name of item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) unsigned int index; /* index of item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct snd_ctl_elem_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) unsigned int offset; /* W: first element ID to get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned int space; /* W: count of element IDs to get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unsigned int used; /* R: count of element IDs set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) unsigned int count; /* R: count of all elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct snd_ctl_elem_id __user *pids; /* R: IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned char reserved[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct snd_ctl_elem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct snd_ctl_elem_id id; /* W: element ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) snd_ctl_elem_type_t type; /* R: value type - SNDRV_CTL_ELEM_TYPE_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) unsigned int access; /* R: value access (bitmask) - SNDRV_CTL_ELEM_ACCESS_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) unsigned int count; /* count of values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) __kernel_pid_t owner; /* owner's PID of this control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) long min; /* R: minimum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) long max; /* R: maximum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) long step; /* R: step (0 variable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) } integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) long long min; /* R: minimum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) long long max; /* R: maximum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) long long step; /* R: step (0 variable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) } integer64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) unsigned int items; /* R: number of items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned int item; /* W: item number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) char name[64]; /* R: value name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) __u64 names_ptr; /* W: names list (ELEM_ADD only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) unsigned int names_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) } enumerated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) unsigned char reserved[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) } value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) unsigned char reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct snd_ctl_elem_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct snd_ctl_elem_id id; /* W: element ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) unsigned int indirect: 1; /* W: indirect access - obsoleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) long value[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) long *value_ptr; /* obsoleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) long long value[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) long long *value_ptr; /* obsoleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } integer64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) unsigned int item[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned int *item_ptr; /* obsoleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) } enumerated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned char data[512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unsigned char *data_ptr; /* obsoleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct snd_aes_iec958 iec958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) } value; /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) unsigned char reserved[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct snd_ctl_tlv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unsigned int numid; /* control element numeric identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) unsigned int length; /* in bytes aligned to 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) unsigned int tlv[0]; /* first TLV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * Read interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) enum sndrv_ctl_event_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) SNDRV_CTL_EVENT_ELEM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define SNDRV_CTL_EVENT_MASK_VALUE (1<<0) /* element value was changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define SNDRV_CTL_EVENT_MASK_INFO (1<<1) /* element info was changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define SNDRV_CTL_EVENT_MASK_ADD (1<<2) /* element was added */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define SNDRV_CTL_EVENT_MASK_TLV (1<<3) /* element TLV tree was changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) /* element was removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct snd_ctl_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int type; /* event type - SNDRV_CTL_EVENT_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct snd_ctl_elem_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) } elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) unsigned char data8[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * Control names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define SNDRV_CTL_NAME_NONE ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define SNDRV_CTL_NAME_PLAYBACK "Playback "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define SNDRV_CTL_NAME_CAPTURE "Capture "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define SNDRV_CTL_NAME_IEC958_NONE ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define SNDRV_CTL_NAME_IEC958_MASK "Mask"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #endif /* _UAPI__SOUND_ASOUND_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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