Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012-2016 VMware, Inc.  All rights reserved.
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * modify it under the terms of EITHER the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * version 2 as published by the Free Software Foundation or the BSD
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #ifndef __VMW_PVRDMA_ABI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define __VMW_PVRDMA_ABI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PVRDMA_UVERBS_ABI_VERSION	3		/* ABI Version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PVRDMA_UAR_HANDLE_MASK		0x00FFFFFF	/* Bottom 24 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PVRDMA_UAR_QP_OFFSET		0		/* QP doorbell. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PVRDMA_UAR_QP_SEND		(1 << 30)	/* Send bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PVRDMA_UAR_QP_RECV		(1 << 31)	/* Recv bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PVRDMA_UAR_CQ_OFFSET		4		/* CQ doorbell. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PVRDMA_UAR_CQ_ARM_SOL		(1 << 29)	/* Arm solicited bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PVRDMA_UAR_CQ_ARM		(1 << 30)	/* Arm bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PVRDMA_UAR_CQ_POLL		(1 << 31)	/* Poll bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PVRDMA_UAR_SRQ_OFFSET		8		/* SRQ doorbell. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PVRDMA_UAR_SRQ_RECV		(1 << 30)	/* Recv bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) enum pvrdma_wr_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	PVRDMA_WR_RDMA_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	PVRDMA_WR_RDMA_WRITE_WITH_IMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	PVRDMA_WR_SEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	PVRDMA_WR_SEND_WITH_IMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	PVRDMA_WR_RDMA_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	PVRDMA_WR_ATOMIC_CMP_AND_SWP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	PVRDMA_WR_LSO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	PVRDMA_WR_SEND_WITH_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	PVRDMA_WR_RDMA_READ_WITH_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	PVRDMA_WR_LOCAL_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	PVRDMA_WR_FAST_REG_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	PVRDMA_WR_BIND_MW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	PVRDMA_WR_REG_SIG_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	PVRDMA_WR_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) enum pvrdma_wc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	PVRDMA_WC_SUCCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	PVRDMA_WC_LOC_LEN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	PVRDMA_WC_LOC_QP_OP_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	PVRDMA_WC_LOC_EEC_OP_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	PVRDMA_WC_LOC_PROT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	PVRDMA_WC_WR_FLUSH_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	PVRDMA_WC_MW_BIND_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	PVRDMA_WC_BAD_RESP_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	PVRDMA_WC_LOC_ACCESS_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	PVRDMA_WC_REM_INV_REQ_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PVRDMA_WC_REM_ACCESS_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	PVRDMA_WC_REM_OP_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PVRDMA_WC_RETRY_EXC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	PVRDMA_WC_RNR_RETRY_EXC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	PVRDMA_WC_LOC_RDD_VIOL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	PVRDMA_WC_REM_INV_RD_REQ_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	PVRDMA_WC_REM_ABORT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	PVRDMA_WC_INV_EECN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	PVRDMA_WC_INV_EEC_STATE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	PVRDMA_WC_FATAL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	PVRDMA_WC_RESP_TIMEOUT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	PVRDMA_WC_GENERAL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum pvrdma_wc_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	PVRDMA_WC_SEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	PVRDMA_WC_RDMA_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	PVRDMA_WC_RDMA_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	PVRDMA_WC_COMP_SWAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	PVRDMA_WC_FETCH_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	PVRDMA_WC_BIND_MW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	PVRDMA_WC_LSO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	PVRDMA_WC_LOCAL_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	PVRDMA_WC_FAST_REG_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	PVRDMA_WC_MASKED_COMP_SWAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	PVRDMA_WC_MASKED_FETCH_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	PVRDMA_WC_RECV = 1 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	PVRDMA_WC_RECV_RDMA_WITH_IMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum pvrdma_wc_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	PVRDMA_WC_GRH			= 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	PVRDMA_WC_WITH_IMM		= 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	PVRDMA_WC_WITH_INVALIDATE	= 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	PVRDMA_WC_IP_CSUM_OK		= 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	PVRDMA_WC_WITH_SMAC		= 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	PVRDMA_WC_WITH_VLAN		= 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	PVRDMA_WC_WITH_NETWORK_HDR_TYPE	= 1 << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	PVRDMA_WC_FLAGS_MAX		= PVRDMA_WC_WITH_NETWORK_HDR_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum pvrdma_network_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	PVRDMA_NETWORK_IB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	PVRDMA_NETWORK_ROCE_V1 = PVRDMA_NETWORK_IB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	PVRDMA_NETWORK_IPV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	PVRDMA_NETWORK_IPV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pvrdma_alloc_ucontext_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	__u32 qp_tab_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct pvrdma_alloc_pd_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	__u32 pdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pvrdma_create_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	__aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	__u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct pvrdma_create_cq_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	__u32 cqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct pvrdma_resize_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	__aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	__u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pvrdma_create_srq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	__aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	__u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct pvrdma_create_srq_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	__u32 srqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pvrdma_create_qp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	__aligned_u64 rbuf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	__aligned_u64 sbuf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	__u32 rbuf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	__u32 sbuf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__aligned_u64 qp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct pvrdma_create_qp_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	__u32 qpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	__u32 qp_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* PVRDMA masked atomic compare and swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct pvrdma_ex_cmp_swap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	__aligned_u64 swap_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	__aligned_u64 compare_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	__aligned_u64 swap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	__aligned_u64 compare_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* PVRDMA masked atomic fetch and add */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct pvrdma_ex_fetch_add {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	__aligned_u64 add_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	__aligned_u64 field_boundary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* PVRDMA address vector. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct pvrdma_av {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	__u32 port_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	__u32 sl_tclass_flowlabel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	__u8 dgid[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	__u8 src_path_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	__u8 gid_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	__u8 stat_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	__u8 hop_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	__u8 dmac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	__u8 reserved[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* PVRDMA scatter/gather entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct pvrdma_sge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	__aligned_u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	__u32   length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	__u32   lkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* PVRDMA receive queue work request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct pvrdma_rq_wqe_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	__aligned_u64 wr_id;		/* wr id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	__u32 num_sge;		/* size of s/g array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	__u32 total_len;	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Use pvrdma_sge (ib_sge) for receive queue s/g array elements. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* PVRDMA send queue work request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pvrdma_sq_wqe_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	__aligned_u64 wr_id;		/* wr id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	__u32 num_sge;		/* size of s/g array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	__u32 total_len;	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	__u32 opcode;		/* operation type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	__u32 send_flags;	/* wr flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		__be32 imm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		__u32 invalidate_rkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	} ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			__aligned_u64 remote_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			__u32 rkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			__u8 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		} rdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			__aligned_u64 remote_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			__aligned_u64 compare_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			__aligned_u64 swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			__u32 rkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		} atomic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			__aligned_u64 remote_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			__u32 log_arg_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			__u32 rkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				struct pvrdma_ex_cmp_swap  cmp_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				struct pvrdma_ex_fetch_add fetch_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			} wr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		} masked_atomics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			__aligned_u64 iova_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			__aligned_u64 pl_pdir_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			__u32 page_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			__u32 page_list_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			__u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			__u32 access_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			__u32 rkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		} fast_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			__u32 remote_qpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			__u32 remote_qkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			struct pvrdma_av av;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		} ud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	} wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Use pvrdma_sge (ib_sge) for send queue s/g array elements. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Completion queue element. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct pvrdma_cqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	__aligned_u64 wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	__aligned_u64 qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	__u32 opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	__u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	__u32 byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	__be32 imm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	__u32 src_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	__u32 wc_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	__u32 vendor_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	__u16 pkey_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	__u16 slid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	__u8 sl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	__u8 dlid_path_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	__u8 port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	__u8 smac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	__u8 network_hdr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	__u8 reserved2[6]; /* Pad to next power of 2 (64). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif /* __VMW_PVRDMA_ABI_H__ */