^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef MLX5_ABI_USER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MLX5_ABI_USER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/if_ether.h> /* For ETH_ALEN. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <rdma/ib_user_ioctl_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MLX5_QP_FLAG_SIGNATURE = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Increment this value if any changes that break userspace ABI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * compatibility are made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MLX5_IB_UVERBS_ABI_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Make sure that all structs defined in this file remain laid out so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * that they pack the same way on 32-bit and 64-bit architectures (to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * avoid incompatibility between 32-bit userspace and 64-bit kernels).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * In particular do not use pointer types -- pass pointers in __u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mlx5_ib_alloc_ucontext_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __u32 total_num_bfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __u32 num_low_latency_bfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum mlx5_lib_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum mlx5_ib_alloc_uctx_v2_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mlx5_ib_alloc_ucontext_req_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __u32 total_num_bfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u32 num_low_latency_bfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __u8 max_cqe_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __u8 reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __aligned_u64 lib_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum mlx5_ib_alloc_ucontext_resp_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum mlx5_user_cmds_supp_uhw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* The eth_min_inline response value is set to off-by-one vs the FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * returned value to allow user-space to deal with older kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum mlx5_user_inline_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MLX5_USER_INLINE_MODE_NA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MLX5_USER_INLINE_MODE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MLX5_USER_INLINE_MODE_L2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MLX5_USER_INLINE_MODE_IP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MLX5_USER_INLINE_MODE_TCP_UDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mlx5_ib_alloc_ucontext_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __u32 qp_tab_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __u32 bf_reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __u32 tot_bfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __u32 cache_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __u16 max_sq_desc_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __u16 max_rq_desc_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __u32 max_send_wqebb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __u32 max_recv_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __u32 max_srq_recv_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __u16 num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __u16 flow_action_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __u32 response_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __u8 cqe_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __u8 cmds_supp_uhw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __u8 eth_min_inline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __u8 clock_info_versions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __aligned_u64 hca_core_clock_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __u32 log_uar_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __u32 num_uars_per_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __u32 num_dyn_bfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __u32 dump_fill_mkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct mlx5_ib_alloc_pd_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __u32 pdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mlx5_ib_tso_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __u32 max_tso; /* Maximum tso payload size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Corresponding bit will be set if qp type from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 'enum ib_qp_type' is supported, e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * supported_qpts |= 1 << IB_QPT_UD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __u32 supported_qpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mlx5_ib_rss_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __u8 reserved[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum mlx5_ib_cqe_comp_res_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct mlx5_ib_cqe_comp_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __u32 max_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) enum mlx5_ib_packet_pacing_cap_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct mlx5_packet_pacing_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __u32 qp_rate_limit_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __u32 qp_rate_limit_max; /* In kpbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Corresponding bit will be set if qp type from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * 'enum ib_qp_type' is supported, e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * supported_qpts |= 1 << IB_QPT_RAW_PACKET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __u32 supported_qpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum mlx5_ib_mpw_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MPW_RESERVED = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MLX5_IB_ALLOW_MPW = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MLX5_IB_SUPPORT_EMPW = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum mlx5_ib_sw_parsing_offloads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MLX5_IB_SW_PARSING = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MLX5_IB_SW_PARSING_CSUM = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MLX5_IB_SW_PARSING_LSO = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct mlx5_ib_sw_parsing_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Corresponding bit will be set if qp type from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * 'enum ib_qp_type' is supported, e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * supported_qpts |= 1 << IB_QPT_RAW_PACKET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __u32 supported_qpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct mlx5_ib_striding_rq_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __u32 min_single_stride_log_num_of_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __u32 max_single_stride_log_num_of_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __u32 min_single_wqe_log_num_of_strides;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __u32 max_single_wqe_log_num_of_strides;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Corresponding bit will be set if qp type from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 'enum ib_qp_type' is supported, e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * supported_qpts |= 1 << IB_QPT_RAW_PACKET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __u32 supported_qpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) enum mlx5_ib_query_dev_resp_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Support 128B CQE compression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum mlx5_ib_tunnel_offloads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct mlx5_ib_query_device_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __u32 response_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct mlx5_ib_tso_caps tso_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct mlx5_ib_rss_caps rss_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct mlx5_packet_pacing_caps packet_pacing_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __u32 mlx5_ib_support_multi_pkt_send_wqes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct mlx5_ib_striding_rq_caps striding_rq_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) enum mlx5_ib_create_cq_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct mlx5_ib_create_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __aligned_u64 db_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __u32 cqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __u8 cqe_comp_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __u8 cqe_comp_res_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __u16 uar_page_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __u16 reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct mlx5_ib_create_cq_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __u32 cqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct mlx5_ib_resize_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __u16 cqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __u16 reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct mlx5_ib_create_srq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) __aligned_u64 db_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) __u32 reserved0; /* explicit padding (optional on i386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) __u32 uidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct mlx5_ib_create_srq_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) __u32 srqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct mlx5_ib_create_qp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) __aligned_u64 db_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __u32 sq_wqe_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __u32 rq_wqe_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __u32 rq_wqe_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __u32 uidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __u32 bfreg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __aligned_u64 sq_buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __aligned_u64 access_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __u32 ece_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* RX Hash function flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) enum mlx5_rx_hash_function_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * RX Hash flags, these flags allows to set which incoming packet's field should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * participates in RX Hash. Each flag represent certain packet's field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * when the flag is set the field that is represented by the flag will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * participate in RX Hash calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * and *TCP and *UDP flags can't be enabled together on the same QP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum mlx5_rx_hash_fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MLX5_RX_HASH_DST_IPV4 = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MLX5_RX_HASH_DST_IPV6 = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Save bits for future fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MLX5_RX_HASH_INNER = (1UL << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct mlx5_ib_create_qp_rss {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) __u8 rx_key_len; /* valid only for Toeplitz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __u8 reserved[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __u8 rx_hash_key[128]; /* valid only for Toeplitz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum mlx5_ib_create_qp_resp_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct mlx5_ib_create_qp_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __u32 bfreg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __u32 ece_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __u32 tirn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __u32 tisn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __u32 rqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) __u32 sqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __u64 tir_icm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct mlx5_ib_alloc_mw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) __u8 num_klms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) __u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) enum mlx5_ib_create_wq_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct mlx5_ib_create_wq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) __aligned_u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __aligned_u64 db_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __u32 rq_wqe_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) __u32 rq_wqe_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __u32 user_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __u32 single_stride_log_num_of_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) __u32 single_wqe_log_num_of_strides;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) __u32 two_byte_shift_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct mlx5_ib_create_ah_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __u32 response_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __u8 dmac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __u8 reserved[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct mlx5_ib_burst_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) __u32 max_burst_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __u16 typical_pkt_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct mlx5_ib_modify_qp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct mlx5_ib_burst_info burst_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) __u32 ece_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct mlx5_ib_modify_qp_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __u32 response_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __u32 dctn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __u32 ece_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct mlx5_ib_create_wq_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __u32 response_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct mlx5_ib_create_rwq_ind_tbl_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) __u32 response_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct mlx5_ib_modify_wq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __u32 comp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct mlx5_ib_clock_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) __u32 sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) __u32 resv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) __aligned_u64 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __aligned_u64 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __aligned_u64 frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __u32 mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __aligned_u64 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __aligned_u64 overflow_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) enum mlx5_ib_mmap_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MLX5_IB_MMAP_REGULAR_PAGE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MLX5_IB_MMAP_WC_PAGE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MLX5_IB_MMAP_NC_PAGE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* 5 is chosen in order to be compatible with old versions of libmlx5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MLX5_IB_MMAP_CORE_CLOCK = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MLX5_IB_MMAP_ALLOC_WC = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MLX5_IB_MMAP_CLOCK_INFO = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MLX5_IB_MMAP_DEVICE_MEM = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MLX5_IB_CLOCK_INFO_V1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct mlx5_ib_flow_counters_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __u32 description;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) __u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct mlx5_ib_flow_counters_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __u32 ncounters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct mlx5_ib_create_flow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __u32 ncounters_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Following are counters data based on ncounters_data, each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * entry in the data[] should match a corresponding counter object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * that was pointed by a counters spec upon the flow creation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct mlx5_ib_flow_counters_data data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #endif /* MLX5_ABI_USER_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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