^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx SD-FEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver is developed for SDFEC16 IP. It provides a char device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * in sysfs and supports file operations like open(), close() and ioctl().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __XILINX_SDFEC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __XILINX_SDFEC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Shared LDPC Tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x10400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x19000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x28000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* LDPC tables depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XSDFEC_SC_TABLE_DEPTH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) (XSDFEC_LDPC_SC_TABLE_ADDR_HIGH - XSDFEC_LDPC_SC_TABLE_ADDR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XSDFEC_LA_TABLE_DEPTH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) (XSDFEC_LDPC_LA_TABLE_ADDR_HIGH - XSDFEC_LDPC_LA_TABLE_ADDR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XSDFEC_QC_TABLE_DEPTH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) (XSDFEC_LDPC_QC_TABLE_ADDR_HIGH - XSDFEC_LDPC_QC_TABLE_ADDR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * enum xsdfec_code - Code Type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @XSDFEC_TURBO_CODE: Driver is configured for Turbo mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @XSDFEC_LDPC_CODE: Driver is configured for LDPC mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * This enum is used to indicate the mode of the driver. The mode is determined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * by checking which codes are set in the driver. Note that the mode cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * changed by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum xsdfec_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) XSDFEC_TURBO_CODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) XSDFEC_LDPC_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * enum xsdfec_order - Order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @XSDFEC_MAINTAIN_ORDER: Maintain order execution of blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @XSDFEC_OUT_OF_ORDER: Out-of-order execution of blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * This enum is used to indicate whether the order of blocks can change from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * input to output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum xsdfec_order {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) XSDFEC_MAINTAIN_ORDER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) XSDFEC_OUT_OF_ORDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * enum xsdfec_turbo_alg - Turbo Algorithm Type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @XSDFEC_MAX_SCALE: Max Log-Map algorithm with extrinsic scaling. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * scaling is set to this is equivalent to the Max Log-Map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @XSDFEC_MAX_STAR: Log-Map algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @XSDFEC_TURBO_ALG_MAX: Used to indicate out of bound Turbo algorithms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * This enum specifies which Turbo Decode algorithm is in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum xsdfec_turbo_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) XSDFEC_MAX_SCALE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) XSDFEC_MAX_STAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) XSDFEC_TURBO_ALG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * enum xsdfec_state - State.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @XSDFEC_INIT: Driver is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @XSDFEC_STARTED: Driver is started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @XSDFEC_STOPPED: Driver is stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @XSDFEC_NEEDS_RESET: Driver needs to be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @XSDFEC_PL_RECONFIGURE: Programmable Logic needs to be recofigured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * This enum is used to indicate the state of the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum xsdfec_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) XSDFEC_INIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) XSDFEC_STARTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) XSDFEC_STOPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) XSDFEC_NEEDS_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) XSDFEC_PL_RECONFIGURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * enum xsdfec_axis_width - AXIS_WIDTH.DIN Setting for 128-bit width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @XSDFEC_1x128b: DIN data input stream consists of a 128-bit lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @XSDFEC_2x128b: DIN data input stream consists of two 128-bit lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @XSDFEC_4x128b: DIN data input stream consists of four 128-bit lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * This enum is used to indicate the AXIS_WIDTH.DIN setting for 128-bit width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * The number of lanes of the DIN data input stream depends upon the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * AXIS_WIDTH.DIN parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum xsdfec_axis_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) XSDFEC_1x128b = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) XSDFEC_2x128b = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) XSDFEC_4x128b = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * enum xsdfec_axis_word_include - Words Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @XSDFEC_FIXED_VALUE: Fixed, the DIN_WORDS AXI4-Stream interface is removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * from the IP instance and is driven with the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * number of words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @XSDFEC_IN_BLOCK: In Block, configures the IP instance to expect a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * DIN_WORDS value per input code block. The DIN_WORDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * interface is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @XSDFEC_PER_AXI_TRANSACTION: Per Transaction, configures the IP instance to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * expect one DIN_WORDS value per input transaction on the DIN interface. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * DIN_WORDS interface is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @XSDFEC_AXIS_WORDS_INCLUDE_MAX: Used to indicate out of bound Words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * This enum is used to specify the DIN_WORDS configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum xsdfec_axis_word_include {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) XSDFEC_FIXED_VALUE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) XSDFEC_IN_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) XSDFEC_PER_AXI_TRANSACTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) XSDFEC_AXIS_WORDS_INCLUDE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * struct xsdfec_turbo - User data for Turbo codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @alg: Specifies which Turbo decode algorithm to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @scale: Specifies the extrinsic scaling to apply when the Max Scale algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * has been selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Turbo code structure to communicate parameters to XSDFEC driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct xsdfec_turbo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __u32 alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __u8 scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * struct xsdfec_ldpc_params - User data for LDPC codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @n: Number of code word bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @k: Number of information bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @psize: Size of sub-matrix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @nlayers: Number of layers in code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @nqc: Quasi Cyclic Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @nmqc: Number of M-sized QC operations in parity check matrix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @nm: Number of M-size vectors in N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @norm_type: Normalization required or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @no_packing: Determines if multiple QC ops should be performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @special_qc: Sub-Matrix property for Circulant weight > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @no_final_parity: Decide if final parity check needs to be performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @max_schedule: Experimental code word scheduling limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @sc_off: SC offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @la_off: LA offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @qc_off: QC offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @sc_table: Pointer to SC Table which must be page aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @la_table: Pointer to LA Table which must be page aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @qc_table: Pointer to QC Table which must be page aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @code_id: LDPC Code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * This structure describes the LDPC code that is passed to the driver by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * application.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct xsdfec_ldpc_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __u32 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __u32 k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __u32 psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __u32 nlayers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __u32 nqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __u32 nmqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __u32 nm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __u32 norm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __u32 no_packing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __u32 special_qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __u32 no_final_parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __u32 max_schedule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __u32 sc_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __u32 la_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __u32 qc_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __u32 *sc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __u32 *la_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __u32 *qc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __u16 code_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * struct xsdfec_status - Status of SD-FEC core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @state: State of the SD-FEC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @activity: Describes if the SD-FEC instance is Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct xsdfec_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __s8 activity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * struct xsdfec_irq - Enabling or Disabling Interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @enable_isr: If true enables the ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @enable_ecc_isr: If true enables the ECC ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct xsdfec_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __s8 enable_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __s8 enable_ecc_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * struct xsdfec_config - Configuration of SD-FEC core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @code: The codes being used by the SD-FEC instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @order: Order of Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @din_width: Width of the DIN AXI4-Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @din_word_include: How DIN_WORDS are inputted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @dout_width: Width of the DOUT AXI4-Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @dout_word_include: HOW DOUT_WORDS are outputted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @irq: Enabling or disabling interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @bypass: Is the core being bypassed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @code_wr_protect: Is write protection of LDPC codes enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct xsdfec_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __u32 order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __u32 din_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __u32 din_word_include;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __u32 dout_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __u32 dout_word_include;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct xsdfec_irq irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __s8 bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __s8 code_wr_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * struct xsdfec_stats - Stats retrived by ioctl XSDFEC_GET_STATS. Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * to buffer atomic_t variables from struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * xsdfec_dev. Counts are accumulated until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * the user clears them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @isr_err_count: Count of ISR errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @cecc_count: Count of Correctable ECC errors (SBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @uecc_count: Count of Uncorrectable ECC errors (MBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct xsdfec_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __u32 isr_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __u32 cecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __u32 uecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * struct xsdfec_ldpc_param_table_sizes - Used to store sizes of SD-FEC table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * entries for an individual LPDC code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @sc_size: Size of SC table used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @la_size: Size of LA table used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @qc_size: Size of QC table used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct xsdfec_ldpc_param_table_sizes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __u32 sc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __u32 la_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __u32 qc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * XSDFEC IOCTL List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define XSDFEC_MAGIC 'f'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * DOC: XSDFEC_START_DEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * ioctl to start SD-FEC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * This fails if the XSDFEC_SET_ORDER ioctl has not been previously called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define XSDFEC_START_DEV _IO(XSDFEC_MAGIC, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * DOC: XSDFEC_STOP_DEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * ioctl to stop the SD-FEC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define XSDFEC_STOP_DEV _IO(XSDFEC_MAGIC, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * DOC: XSDFEC_GET_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * ioctl that returns status of SD-FEC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define XSDFEC_GET_STATUS _IOR(XSDFEC_MAGIC, 2, struct xsdfec_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * DOC: XSDFEC_SET_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @struct xsdfec_irq *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Pointer to the &struct xsdfec_irq that contains the interrupt settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * for the SD-FEC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * ioctl to enable or disable irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define XSDFEC_SET_IRQ _IOW(XSDFEC_MAGIC, 3, struct xsdfec_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * DOC: XSDFEC_SET_TURBO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @struct xsdfec_turbo *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Pointer to the &struct xsdfec_turbo that contains the Turbo decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * settings for the SD-FEC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * ioctl that sets the SD-FEC Turbo parameter values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * This can only be used when the driver is in the XSDFEC_STOPPED state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 4, struct xsdfec_turbo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * DOC: XSDFEC_ADD_LDPC_CODE_PARAMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @struct xsdfec_ldpc_params *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Pointer to the &struct xsdfec_ldpc_params that contains the LDPC code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * parameters to be added to the SD-FEC Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * ioctl to add an LDPC code to the SD-FEC LDPC codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * This can only be used when:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * - Driver is in the XSDFEC_STOPPED state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * - SD-FEC core is configured as LPDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * - SD-FEC Code Write Protection is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define XSDFEC_ADD_LDPC_CODE_PARAMS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) _IOW(XSDFEC_MAGIC, 5, struct xsdfec_ldpc_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * DOC: XSDFEC_GET_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @struct xsdfec_config *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Pointer to the &struct xsdfec_config that contains the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * configuration settings of the SD-FEC Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * ioctl that returns SD-FEC core configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define XSDFEC_GET_CONFIG _IOR(XSDFEC_MAGIC, 6, struct xsdfec_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * DOC: XSDFEC_GET_TURBO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @struct xsdfec_turbo *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Pointer to the &struct xsdfec_turbo that contains the current Turbo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * decode settings of the SD-FEC Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * ioctl that returns SD-FEC turbo param values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define XSDFEC_GET_TURBO _IOR(XSDFEC_MAGIC, 7, struct xsdfec_turbo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * DOC: XSDFEC_SET_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @struct unsigned long *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Pointer to the unsigned long that contains a value from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @enum xsdfec_order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * ioctl that sets order, if order of blocks can change from input to output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * This can only be used when the driver is in the XSDFEC_STOPPED state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define XSDFEC_SET_ORDER _IOW(XSDFEC_MAGIC, 8, unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * DOC: XSDFEC_SET_BYPASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @struct bool *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Pointer to bool that sets the bypass value, where false results in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * normal operation and false results in the SD-FEC performing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * configured operations (same number of cycles) but output data matches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * the input data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * ioctl that sets bypass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * This can only be used when the driver is in the XSDFEC_STOPPED state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define XSDFEC_SET_BYPASS _IOW(XSDFEC_MAGIC, 9, bool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * DOC: XSDFEC_IS_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @struct bool *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Pointer to bool that returns true if the SD-FEC is processing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * ioctl that determines if SD-FEC is processing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define XSDFEC_IS_ACTIVE _IOR(XSDFEC_MAGIC, 10, bool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * DOC: XSDFEC_CLEAR_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * ioctl that clears error stats collected during interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define XSDFEC_CLEAR_STATS _IO(XSDFEC_MAGIC, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * DOC: XSDFEC_GET_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * @Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * @struct xsdfec_stats *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Pointer to the &struct xsdfec_stats that will contain the updated stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * ioctl that returns SD-FEC core stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * This can only be used when the driver is in the XSDFEC_STOPPED state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define XSDFEC_GET_STATS _IOR(XSDFEC_MAGIC, 12, struct xsdfec_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * DOC: XSDFEC_SET_DEFAULT_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * ioctl that returns SD-FEC core to default config, use after a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * This can only be used when the driver is in the XSDFEC_STOPPED state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define XSDFEC_SET_DEFAULT_CONFIG _IO(XSDFEC_MAGIC, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #endif /* __XILINX_SDFEC_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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