^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip HDCP Host Library driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HL_DRIVER_ALLOCATE_DYNAMIC_MEM 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) // hl_drv_ioctl numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) HL_DRV_NR_MIN = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) HL_DRV_NR_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) HL_DRV_NR_MEMINFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) HL_DRV_NR_LOAD_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) HL_DRV_NR_READ_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) HL_DRV_NR_WRITE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) HL_DRV_NR_MEMSET_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) HL_DRV_NR_READ_HPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) HL_DRV_NR_WRITE_HPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RK_DRV_NR_GET_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK_DRV_NR_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) HL_DRV_NR_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HL_DRV_IOC_INIT: associate file descriptor with the indicated memory. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * must be called before any other hl_drv_ioctl on the file descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * - hpi_base = base address of HPI registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - code_base = base address of firmware memory (0 to allocate internally)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - data_base = base address of data memory (0 to allocate internally)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * - code_len, data_len = length of firmware and data memory, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HL_DRV_IOC_INIT _IOW('H', HL_DRV_NR_INIT, struct hl_drv_ioc_meminfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * HL_DRV_IOC_MEMINFO: retrieve memory information from file descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Fills out the meminfo struct, returning the values passed to HL_DRV_IOC_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * except that the actual base addresses of internal allocations (if any) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * reported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HL_DRV_IOC_MEMINFO _IOR('H', HL_DRV_NR_MEMINFO, struct hl_drv_ioc_meminfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct hl_drv_ioc_meminfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __u32 hpi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __u32 code_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __u32 code_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __u32 data_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __u32 data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * HL_DRV_IOC_LOAD_CODE: write the provided buffer to the firmware memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * - len = number of bytes in data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * - data = data to write to firmware memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * This can only be done once (successfully). Subsequent attempts will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * return -EBUSY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HL_DRV_IOC_LOAD_CODE _IOW('H', HL_DRV_NR_LOAD_CODE, struct hl_drv_ioc_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct hl_drv_ioc_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * HL_DRV_IOC_READ_DATA: copy from data memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * HL_DRV_IOC_WRITE_DATA: copy to data memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * - offset = start copying at this byte offset into the data memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * - len = number of bytes to copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * - data = for write, buffer containing data to copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * for read, buffer to which read data will be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HL_DRV_IOC_READ_DATA _IOWR('H', HL_DRV_NR_READ_DATA, struct hl_drv_ioc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HL_DRV_IOC_WRITE_DATA _IOW('H', HL_DRV_NR_WRITE_DATA, struct hl_drv_ioc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * HL_DRV_IOC_MEMSET_DATA: initialize data memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * - offset = start initializatoin at this byte offset into the data memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * - len = number of bytes to set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * - data[0] = byte value to write to all indicated memory locations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HL_DRV_IOC_MEMSET_DATA _IOW('H', HL_DRV_NR_MEMSET_DATA, struct hl_drv_ioc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct hl_drv_ioc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * HL_DRV_IOC_READ_HPI: read HPI register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * HL_DRV_IOC_WRITE_HPI: write HPI register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * - offset = byte offset of HPI register to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * - value = for write, value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * for read, location to which result is stored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HL_DRV_IOC_READ_HPI _IOWR('H', HL_DRV_NR_READ_HPI, struct hl_drv_ioc_hpi_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HL_DRV_IOC_WRITE_HPI _IOW('H', HL_DRV_NR_WRITE_HPI, struct hl_drv_ioc_hpi_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct hl_drv_ioc_hpi_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RK_DRV_IOC_GET_STATUS _IOR('H', RK_DRV_NR_GET_STATUS, struct hl_drv_ioc_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct hl_drv_ioc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __u32 connected_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __u32 booted_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RK_DRV_IOC_RESET _IOR('H', RK_DRV_NR_RESET, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif // _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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