Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2014 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * as published by the Free Software Foundation; either version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * 2 of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef _UAPI_MISC_CXL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _UAPI_MISC_CXL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct cxl_ioctl_start_work {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	__u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	__u64 work_element_descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	__u64 amr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	__s16 num_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	__u16 tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	__s32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	__u64 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	__u64 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	__u64 reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	__u64 reserved5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CXL_START_WORK_AMR		0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CXL_START_WORK_NUM_IRQS		0x0000000000000002ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CXL_START_WORK_ERR_FF		0x0000000000000004ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CXL_START_WORK_TID		0x0000000000000008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CXL_START_WORK_ALL		(CXL_START_WORK_AMR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 					 CXL_START_WORK_NUM_IRQS |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 					 CXL_START_WORK_ERR_FF |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 					 CXL_START_WORK_TID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Possible modes that an afu can be in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CXL_MODE_DEDICATED   0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CXL_MODE_DIRECTED    0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* possible flags for the cxl_afu_id flags field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CXL_AFUID_FLAG_SLAVE    0x1  /* In directed-mode afu is in slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct cxl_afu_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	__u64 flags;     /* One of CXL_AFUID_FLAG_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	__u32 card_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	__u32 afu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	__u32 afu_mode;  /* one of the CXL_MODE_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	__u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	__u64 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	__u64 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	__u64 reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	__u64 reserved5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	__u64 reserved6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* base adapter image header is included in the image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CXL_AI_NEED_HEADER	0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CXL_AI_ALL		CXL_AI_NEED_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CXL_AI_HEADER_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CXL_AI_BUFFER_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CXL_AI_MAX_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CXL_AI_MAX_CHUNK_SIZE (CXL_AI_BUFFER_SIZE * CXL_AI_MAX_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct cxl_adapter_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	__u64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	__u64 len_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__u64 len_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__u64 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__u64 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__u64 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	__u64 reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* ioctl numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CXL_MAGIC 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* AFU devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CXL_IOCTL_START_WORK		_IOW(CXL_MAGIC, 0x00, struct cxl_ioctl_start_work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CXL_IOCTL_GET_PROCESS_ELEMENT	_IOR(CXL_MAGIC, 0x01, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CXL_IOCTL_GET_AFU_ID            _IOR(CXL_MAGIC, 0x02, struct cxl_afu_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* adapter devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CXL_IOCTL_DOWNLOAD_IMAGE        _IOW(CXL_MAGIC, 0x0A, struct cxl_adapter_image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CXL_IOCTL_VALIDATE_IMAGE        _IOW(CXL_MAGIC, 0x0B, struct cxl_adapter_image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CXL_READ_MIN_SIZE 0x1000 /* 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* Events from read() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) enum cxl_event_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	CXL_EVENT_RESERVED      = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	CXL_EVENT_AFU_INTERRUPT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	CXL_EVENT_DATA_STORAGE  = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	CXL_EVENT_AFU_ERROR     = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	CXL_EVENT_AFU_DRIVER    = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct cxl_event_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	__u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	__u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	__u16 process_element;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	__u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct cxl_event_afu_interrupt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	__u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	__u16 irq; /* Raised AFU interrupt number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	__u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct cxl_event_data_storage {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	__u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	__u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	__u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	__u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	__u64 dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	__u64 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct cxl_event_afu_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	__u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	__u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	__u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	__u64 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct cxl_event_afu_driver_reserved {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * Defines the buffer passed to the cxl driver by the AFU driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * This is not ABI since the event header.size passed to the user for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * existing events is set in the read call to sizeof(cxl_event_header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * + sizeof(whatever event is being dispatched) and the user is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * required to use a 4K buffer on the read call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * Of course the contents will be ABI, but that's up the AFU driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	__u32 data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct cxl_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct cxl_event_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		struct cxl_event_afu_interrupt irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		struct cxl_event_data_storage fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		struct cxl_event_afu_error afu_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		struct cxl_event_afu_driver_reserved afu_driver_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* _UAPI_MISC_CXL_H */