^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * "Software"), to deal in the Software without restriction, including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * without limitation the rights to use, copy, modify, merge, publish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * distribute, sub license, and/or sell copies of the Software, and to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * permit persons to whom the Software is furnished to do so, subject to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * The above copyright notice and this permission notice (including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * next paragraph) shall be included in all copies or substantial portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * USE OR OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef __VMWGFX_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define __VMWGFX_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRM_VMW_MAX_SURFACE_FACES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRM_VMW_MAX_MIP_LEVELS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRM_VMW_GET_PARAM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRM_VMW_ALLOC_DMABUF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRM_VMW_ALLOC_BO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRM_VMW_UNREF_DMABUF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRM_VMW_HANDLE_CLOSE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRM_VMW_CURSOR_BYPASS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRM_VMW_CONTROL_STREAM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRM_VMW_CLAIM_STREAM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRM_VMW_UNREF_STREAM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* guarded by DRM_VMW_PARAM_3D == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRM_VMW_CREATE_CONTEXT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DRM_VMW_UNREF_CONTEXT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRM_VMW_CREATE_SURFACE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRM_VMW_UNREF_SURFACE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRM_VMW_REF_SURFACE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DRM_VMW_EXECBUF 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DRM_VMW_GET_3D_CAP 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DRM_VMW_FENCE_WAIT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRM_VMW_FENCE_SIGNALED 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRM_VMW_FENCE_UNREF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRM_VMW_FENCE_EVENT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRM_VMW_PRESENT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRM_VMW_PRESENT_READBACK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRM_VMW_UPDATE_LAYOUT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRM_VMW_CREATE_SHADER 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRM_VMW_UNREF_SHADER 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRM_VMW_GB_SURFACE_CREATE 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRM_VMW_GB_SURFACE_REF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRM_VMW_SYNCCPU 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRM_VMW_GB_SURFACE_CREATE_EXT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRM_VMW_GB_SURFACE_REF_EXT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DRM_VMW_MSG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * DRM_VMW_GET_PARAM - get device information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * DRM_VMW_PARAM_FIFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Offset to use to map the first page of the FIFO read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * The fifo is mapped using the mmap() system call on the drm device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * DRM_VMW_PARAM_OVERLAY_IOCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Does the driver support the overlay ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * DRM_VMW_PARAM_SM4_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * SM4_1 support is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * DRM_VMW_PARAM_SM5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * SM5 support is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DRM_VMW_PARAM_NUM_STREAMS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DRM_VMW_PARAM_3D 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DRM_VMW_PARAM_HW_CAPS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DRM_VMW_PARAM_FIFO_CAPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DRM_VMW_PARAM_MAX_FB_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRM_VMW_PARAM_FIFO_HW_VERSION 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRM_VMW_PARAM_3D_CAPS_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRM_VMW_PARAM_MAX_MOB_SIZE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRM_VMW_PARAM_SCREEN_TARGET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRM_VMW_PARAM_DX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRM_VMW_PARAM_HW_CAPS2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRM_VMW_PARAM_SM4_1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRM_VMW_PARAM_SM5 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * enum drm_vmw_handle_type - handle type for ref ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum drm_vmw_handle_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DRM_VMW_HANDLE_LEGACY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DRM_VMW_HANDLE_PRIME = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * struct drm_vmw_getparam_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @value: Returned value. //Out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @param: Parameter to query. //In.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Argument to the DRM_VMW_GET_PARAM Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct drm_vmw_getparam_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __u32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * DRM_VMW_CREATE_CONTEXT - Create a host context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Allocates a device unique context id, and queues a create context command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * for the host. Does not wait for host completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * struct drm_vmw_context_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @cid: Device unique context ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct drm_vmw_context_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __s32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * DRM_VMW_UNREF_CONTEXT - Create a host context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Frees a global context id, and queues a destroy host command for the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Does not wait for host completion. The context ID can be used directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * in the command stream and shows up as the same context ID on the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * DRM_VMW_CREATE_SURFACE - Create a host suface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Allocates a device unique surface id, and queues a create surface command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * for the host. Does not wait for host completion. The surface ID can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * used directly in the command stream and shows up as the same surface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * ID on the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * struct drm_wmv_surface_create_req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @flags: Surface flags as understood by the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @format: Surface format as understood by the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @mip_levels: Number of mip levels for each face.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * An unused face should have 0 encoded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @size_addr: Address of a user-space array of sruct drm_vmw_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * cast to an __u64 for 32-64 bit compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * The size of the array should equal the total number of mipmap levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @shareable: Boolean whether other clients (as identified by file descriptors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * may reference this surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @scanout: Boolean whether the surface is intended to be used as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * scanout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Input data to the DRM_VMW_CREATE_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Output data from the DRM_VMW_REF_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct drm_vmw_surface_create_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __u64 size_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __s32 shareable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __s32 scanout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * struct drm_wmv_surface_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @sid: Surface id of created surface or surface to destroy or reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @handle_type: Handle type for DRM_VMW_REF_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Output data from the DRM_VMW_CREATE_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Input argument to the DRM_VMW_REF_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct drm_vmw_surface_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __s32 sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) enum drm_vmw_handle_type handle_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * struct drm_vmw_size ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @width - mip level width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @height - mip level height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @depth - mip level depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Description of a mip level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Input data to the DRM_WMW_CREATE_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct drm_vmw_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __u32 depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * union drm_vmw_surface_create_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @rep: Output data as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @req: Input data as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Argument to the DRM_VMW_CREATE_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) union drm_vmw_surface_create_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct drm_vmw_surface_arg rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct drm_vmw_surface_create_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * DRM_VMW_REF_SURFACE - Reference a host surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Puts a reference on a host surface with a give sid, as previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * returned by the DRM_VMW_CREATE_SURFACE ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * A reference will make sure the surface isn't destroyed while we hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * it and will allow the calling client to use the surface ID in the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * On successful return, the Ioctl returns the surface information given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * in the DRM_VMW_CREATE_SURFACE ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * union drm_vmw_surface_reference_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @rep: Output data as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @req: Input data as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Argument to the DRM_VMW_REF_SURFACE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) union drm_vmw_surface_reference_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct drm_vmw_surface_create_req rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct drm_vmw_surface_arg req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * DRM_VMW_UNREF_SURFACE - Unreference a host surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Clear a reference previously put on a host surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * When all references are gone, including the one implicitly placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * on creation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * a destroy surface command will be queued for the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Does not wait for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * DRM_VMW_EXECBUF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Submit a command buffer for execution on the host, and return a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * fence seqno that when signaled, indicates that the command buffer has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * struct drm_vmw_execbuf_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @commands: User-space address of a command buffer cast to an __u64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @command-size: Size in bytes of the command buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @throttle-us: Sleep until software is less than @throttle_us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * microseconds ahead of hardware. The driver may round this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * to the nearest kernel tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * __u64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @version: Allows expanding the execbuf ioctl parameters without breaking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * backwards compatibility, since user-space will always tell the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * which version it uses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @flags: Execbuf flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @imported_fence_fd: FD for a fence imported from another device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Argument to the DRM_VMW_EXECBUF Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DRM_VMW_EXECBUF_VERSION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct drm_vmw_execbuf_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __u64 commands;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __u32 command_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __u32 throttle_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) __u64 fence_rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __u32 context_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __s32 imported_fence_fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * struct drm_vmw_fence_rep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @handle: Fence object handle for fence associated with a command submission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @mask: Fence flags relevant for this fence object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @seqno: Fence sequence number in fifo. A fence object with a lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * seqno will signal the EXEC flag before a fence object with a higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * seqno. This can be used by user-space to avoid kernel calls to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * whether a fence has signaled the EXEC flag. Note that @seqno will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * wrap at 32-bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @passed_seqno: The highest seqno number processed by the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * so far. This can be used to mark user-space fence objects as signaled, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * to determine whether a fence seqno might be stale.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @fd: FD associated with the fence, -1 if not exported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @error: This member should've been set to -EFAULT on submission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * The following actions should be take on completion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * error == -EFAULT: Fence communication failed. The host is synchronized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Use the last fence id read from the FIFO fence register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * error != 0 && error != -EFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Fence submission failed. The host is synchronized. Use the fence_seq member.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * error == 0: All is OK, The host may not be synchronized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Use the fence_seq member.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Input / Output data to the DRM_VMW_EXECBUF Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct drm_vmw_fence_rep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __u32 seqno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __u32 passed_seqno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __s32 fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __s32 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * DRM_VMW_ALLOC_BO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Allocate a buffer object that is visible also to the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * NOTE: The buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * identified by a handle and an offset, which are private to the guest, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * useable in the command stream. The guest kernel may translate these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * and patch up the command stream accordingly. In the future, the offset may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * be zero at all times, or it may disappear from the interface before it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * The buffer object may stay user-space mapped in the guest at all times,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * and is thus suitable for sub-allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Buffer objects are mapped using the mmap() syscall on the drm device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * struct drm_vmw_alloc_bo_req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * @size: Required minimum size of the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Input data to the DRM_VMW_ALLOC_BO Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct drm_vmw_alloc_bo_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * struct drm_vmw_bo_rep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @map_handle: Offset to use in the mmap() call used to map the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @handle: Handle unique to this buffer. Used for unreferencing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @cur_gmr_id: GMR id to use in the command stream when this buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * referenced. See not above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @cur_gmr_offset: Offset to use in the command stream when this buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * referenced. See note above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Output data from the DRM_VMW_ALLOC_BO Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct drm_vmw_bo_rep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __u64 map_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) __u32 cur_gmr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __u32 cur_gmr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define drm_vmw_dmabuf_rep drm_vmw_bo_rep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * union drm_vmw_alloc_bo_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * @req: Input data as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * @rep: Output data as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Argument to the DRM_VMW_ALLOC_BO Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) union drm_vmw_alloc_bo_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct drm_vmw_alloc_bo_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct drm_vmw_bo_rep rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * This IOCTL controls the overlay units of the svga device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * The SVGA overlay units does not work like regular hardware units in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * that they do not automaticaly read back the contents of the given dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * buffer. But instead only read back for each call to this ioctl, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * at any point between this call being made and a following call that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * either changes the buffer or disables the stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * struct drm_vmw_rect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Defines a rectangle. Used in the overlay ioctl to define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * source and destination rectangle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct drm_vmw_rect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __s32 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __s32 y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) __u32 h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * struct drm_vmw_control_stream_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * @stream_id: Stearm to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * @enabled: If false all following arguments are ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @handle: Handle to buffer for getting data from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @format: Format of the overlay as understood by the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * @width: Width of the overlay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @height: Height of the overlay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @size: Size of the overlay in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * @pitch: Array of pitches, the two last are only used for YUV12 formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @offset: Offset from start of dma buffer to overlay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @src: Source rect, must be within the defined area above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @dst: Destination rect, x and y may be negative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Argument to the DRM_VMW_CONTROL_STREAM Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct drm_vmw_control_stream_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __u32 stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __u32 enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __u32 color_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __s32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __u32 pitch[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct drm_vmw_rect src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct drm_vmw_rect dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * struct drm_vmw_cursor_bypass_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * @flags: Flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @xpos: X position of cursor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * @ypos: Y position of cursor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * @xhot: X hotspot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * @yhot: Y hotspot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct drm_vmw_cursor_bypass_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __u32 crtc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __s32 xpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __s32 ypos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __s32 xhot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) __s32 yhot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * DRM_VMW_CLAIM_STREAM - Claim a single stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * struct drm_vmw_context_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * @stream_id: Device unique context ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct drm_vmw_stream_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) __u32 stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * DRM_VMW_UNREF_STREAM - Unclaim a stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * Return a single stream that was claimed by this process. Also makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * sure that the stream has been stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * DRM_VMW_GET_3D_CAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Read 3D capabilities from the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * struct drm_vmw_get_3d_cap_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * @buffer: Pointer to a buffer for capability data, cast to an __u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * @size: Max size to copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * ioctls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct drm_vmw_get_3d_cap_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __u64 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __u32 max_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * DRM_VMW_FENCE_WAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * Waits for a fence object to signal. The wait is interruptible, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * signals may be delivered during the interrupt. The wait may timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * in which case the calls returns -EBUSY. If the wait is restarted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * that is restarting without resetting @cookie_valid to zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * the timeout is computed from the first call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * have executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * in the buffer given to the EXECBUF ioctl returning the fence object handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * are available to user-space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * fenc wait ioctl returns 0, the fence object has been unreferenced after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * the wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * struct drm_vmw_fence_wait_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * @cookie_valid: Must be reset to 0 on first call. Left alone on restart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * @kernel_cookie: Set to 0 on first call. Left alone on restart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * @timeout_us: Wait timeout in microseconds. 0 for indefinite timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * @lazy: Set to 1 if timing is not critical. Allow more than a kernel tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * before returning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * @flags: Fence flags to wait on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @wait_options: Options that control the behaviour of the wait ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * Input argument to the DRM_VMW_FENCE_WAIT ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct drm_vmw_fence_wait_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __s32 cookie_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) __u64 kernel_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) __u64 timeout_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) __s32 lazy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) __s32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) __s32 wait_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __s32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * DRM_VMW_FENCE_SIGNALED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Checks if a fence object is signaled..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * struct drm_vmw_fence_signaled_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * @flags: Fence object flags input to DRM_VMW_FENCE_SIGNALED ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * @signaled: Out: Flags signaled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @sequence: Out: Highest sequence passed so far. Can be used to signal the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * EXEC flag of user-space fence objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Input/Output argument to the DRM_VMW_FENCE_SIGNALED and DRM_VMW_FENCE_UNREF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * ioctls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct drm_vmw_fence_signaled_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) __s32 signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __u32 passed_seqno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) __u32 signaled_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * DRM_VMW_FENCE_UNREF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Unreferences a fence object, and causes it to be destroyed if there are no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * other references to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * struct drm_vmw_fence_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * Input/Output argument to the DRM_VMW_FENCE_UNREF ioctl..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct drm_vmw_fence_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * DRM_VMW_FENCE_EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Queues an event on a fence to be delivered on the drm character device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * Optionally the approximate time when the fence signaled is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * given by the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * The event type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct drm_vmw_event_fence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct drm_event base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __u32 tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __u32 tv_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * Flags that may be given to the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Request fence signaled time on the event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * struct drm_vmw_fence_event_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * @fence_rep: Pointer to fence_rep structure cast to __u64 or 0 if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * the fence is not supposed to be referenced by user-space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * @user_info: Info to be delivered with the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * @handle: Attach the event to this fence only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * @flags: A set of flags as defined above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct drm_vmw_fence_event_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __u64 fence_rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * DRM_VMW_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * Executes an SVGA present on a given fb for a given surface. The surface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * is placed on the framebuffer. Cliprects are given relative to the given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * point (the point disignated by dest_{x|y}).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * struct drm_vmw_present_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * @fb_id: framebuffer id to present / read back from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * @sid: Surface id to present from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * @dest_x: X placement coordinate for surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * @dest_y: Y placement coordinate for surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * @clips_ptr: Pointer to an array of clip rects cast to an __u64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * @num_clips: Number of cliprects given relative to the framebuffer origin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * in the same coordinate space as the frame buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * @pad64: Unused 64-bit padding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * Input argument to the DRM_VMW_PRESENT ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct drm_vmw_present_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __u32 fb_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) __u32 sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __s32 dest_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __s32 dest_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) __u64 clips_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __u32 num_clips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * DRM_VMW_PRESENT_READBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Executes an SVGA present readback from a given fb to the dma buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * currently bound as the fb. If there is no dma buffer bound to the fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * an error will be returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * struct drm_vmw_present_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * @fb_id: fb_id to present / read back from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * @num_clips: Number of cliprects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * @clips_ptr: Pointer to an array of clip rects cast to an __u64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an __u64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * If this member is NULL, then the ioctl should not return a fence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct drm_vmw_present_readback_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) __u32 fb_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __u32 num_clips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) __u64 clips_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __u64 fence_rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * DRM_VMW_UPDATE_LAYOUT - Update layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * Updates the preferred modes and connection status for connectors. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * command consists of one drm_vmw_update_layout_arg pointing to an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * of num_outputs drm_vmw_rect's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * struct drm_vmw_update_layout_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * @num_outputs: number of active connectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * @rects: pointer to array of drm_vmw_rect cast to an __u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct drm_vmw_update_layout_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) __u32 num_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) __u64 rects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * DRM_VMW_CREATE_SHADER - Create shader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * Creates a shader and optionally binds it to a dma buffer containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * the shader byte-code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * enum drm_vmw_shader_type - Shader types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) enum drm_vmw_shader_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) drm_vmw_shader_type_vs = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) drm_vmw_shader_type_ps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * struct drm_vmw_shader_create_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * @shader_type: Shader type of the shader to create.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * @size: Size of the byte-code in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * where the shader byte-code starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * @buffer_handle: Buffer handle identifying the buffer containing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * shader byte-code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * @shader_handle: On successful completion contains a handle that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * can be used to subsequently identify the shader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * @offset: Offset in bytes into the buffer given by @buffer_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Input / Output argument to the DRM_VMW_CREATE_SHADER Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct drm_vmw_shader_create_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) enum drm_vmw_shader_type shader_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __u32 buffer_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __u32 shader_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * DRM_VMW_UNREF_SHADER - Unreferences a shader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * Destroys a user-space reference to a shader, optionally destroying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * struct drm_vmw_shader_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * @handle: Handle identifying the shader to destroy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * Input argument to the DRM_VMW_UNREF_SHADER ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct drm_vmw_shader_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * DRM_VMW_GB_SURFACE_CREATE - Create a host guest-backed surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Allocates a surface handle and queues a create surface command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * for the host on the first use of the surface. The surface ID can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * be used as the surface ID in commands referencing the surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * enum drm_vmw_surface_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * @drm_vmw_surface_flag_shareable: Whether the surface is shareable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * @drm_vmw_surface_flag_scanout: Whether the surface is a scanout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * given.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * @drm_vmw_surface_flag_coherent: Back surface with coherent memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) enum drm_vmw_surface_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) drm_vmw_surface_flag_shareable = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) drm_vmw_surface_flag_scanout = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) drm_vmw_surface_flag_create_buffer = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) drm_vmw_surface_flag_coherent = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * struct drm_vmw_gb_surface_create_req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * @svga3d_flags: SVGA3d surface flags for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * @format: SVGA3d format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * @mip_level: Number of mip levels for all faces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * @drm_surface_flags Flags as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * @multisample_count Future use. Set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * @autogen_filter Future use. Set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * @buffer_handle Buffer handle of backup buffer. SVGA3D_INVALID_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * if none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * @base_size Size of the base mip level for all faces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * @array_size Must be zero for non-DX hardware, and if non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * svga3d_flags must have proper bind flags setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Input argument to the DRM_VMW_GB_SURFACE_CREATE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct drm_vmw_gb_surface_create_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) __u32 svga3d_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) __u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) __u32 mip_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) enum drm_vmw_surface_flags drm_surface_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) __u32 multisample_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) __u32 autogen_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) __u32 buffer_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) __u32 array_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct drm_vmw_size base_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * struct drm_vmw_gb_surface_create_rep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * @handle: Surface handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * @backup_size: Size of backup buffers for this surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * @buffer_handle: Handle of backup buffer. SVGA3D_INVALID_ID if none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * @buffer_size: Actual size of the buffer identified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * @buffer_handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * @buffer_map_handle: Offset into device address space for the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * identified by @buffer_handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * Part of output argument for the DRM_VMW_GB_SURFACE_REF ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct drm_vmw_gb_surface_create_rep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) __u32 backup_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) __u32 buffer_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) __u32 buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) __u64 buffer_map_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * union drm_vmw_gb_surface_create_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * @req: Input argument as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * @rep: Output argument as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Argument to the DRM_VMW_GB_SURFACE_CREATE ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) union drm_vmw_gb_surface_create_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct drm_vmw_gb_surface_create_rep rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct drm_vmw_gb_surface_create_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * DRM_VMW_GB_SURFACE_REF - Reference a host surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * Puts a reference on a host surface with a given handle, as previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * returned by the DRM_VMW_GB_SURFACE_CREATE ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * A reference will make sure the surface isn't destroyed while we hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * it and will allow the calling client to use the surface handle in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * the command stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * On successful return, the Ioctl returns the surface information given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * to and returned from the DRM_VMW_GB_SURFACE_CREATE ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * struct drm_vmw_gb_surface_reference_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * @creq: The data used as input when the surface was created, as described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * above at "struct drm_vmw_gb_surface_create_req"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * @crep: Additional data output when the surface was created, as described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * above at "struct drm_vmw_gb_surface_create_rep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * Output Argument to the DRM_VMW_GB_SURFACE_REF ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct drm_vmw_gb_surface_ref_rep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct drm_vmw_gb_surface_create_req creq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct drm_vmw_gb_surface_create_rep crep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * union drm_vmw_gb_surface_reference_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * @req: Input data as described above at "struct drm_vmw_surface_arg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * @rep: Output data as described above at "struct drm_vmw_gb_surface_ref_rep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * Argument to the DRM_VMW_GB_SURFACE_REF Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) union drm_vmw_gb_surface_reference_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct drm_vmw_gb_surface_ref_rep rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct drm_vmw_surface_arg req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * DRM_VMW_SYNCCPU - Sync a DMA buffer / MOB for CPU access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Idles any previously submitted GPU operations on the buffer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * by default blocks command submissions that reference the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * If the file descriptor used to grab a blocking CPU sync is closed, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * cpu sync is released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * The flags argument indicates how the grab / release operation should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * performed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * enum drm_vmw_synccpu_flags - Synccpu flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * @drm_vmw_synccpu_read: Sync for read. If sync is done for read only, it's a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * hint to the kernel to allow command submissions that references the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * for read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * @drm_vmw_synccpu_write: Sync for write. Block all command submissions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * referencing this buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * -EBUSY should the buffer be busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * while the buffer is synced for CPU. This is similar to the GEM bo idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) enum drm_vmw_synccpu_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) drm_vmw_synccpu_read = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) drm_vmw_synccpu_write = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) drm_vmw_synccpu_dontblock = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) drm_vmw_synccpu_allow_cs = (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * enum drm_vmw_synccpu_op - Synccpu operations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * @drm_vmw_synccpu_grab: Grab the buffer for CPU operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * @drm_vmw_synccpu_release: Release a previous grab.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) enum drm_vmw_synccpu_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) drm_vmw_synccpu_grab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) drm_vmw_synccpu_release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * struct drm_vmw_synccpu_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * @op: The synccpu operation as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * @handle: Handle identifying the buffer object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * @flags: Flags as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct drm_vmw_synccpu_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) enum drm_vmw_synccpu_op op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) enum drm_vmw_synccpu_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * DRM_VMW_CREATE_EXTENDED_CONTEXT - Create a host context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * Allocates a device unique context id, and queues a create context command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * for the host. Does not wait for host completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) enum drm_vmw_extended_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) drm_vmw_context_legacy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) drm_vmw_context_dx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * union drm_vmw_extended_context_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * @req: Context type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * @rep: Context identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * Argument to the DRM_VMW_CREATE_EXTENDED_CONTEXT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) union drm_vmw_extended_context_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) enum drm_vmw_extended_context req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct drm_vmw_context_arg rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * DRM_VMW_HANDLE_CLOSE - Close a user-space handle and release its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * underlying resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * Note that this ioctl is overlaid on the deprecated DRM_VMW_UNREF_DMABUF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * struct drm_vmw_handle_close_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * @handle: Handle to close.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * Argument to the DRM_VMW_HANDLE_CLOSE Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct drm_vmw_handle_close_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) __u32 pad64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * DRM_VMW_GB_SURFACE_CREATE_EXT - Create a host guest-backed surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * Allocates a surface handle and queues a create surface command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * for the host on the first use of the surface. The surface ID can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * be used as the surface ID in commands referencing the surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * This new command extends DRM_VMW_GB_SURFACE_CREATE by adding version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * parameter and 64 bit svga flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * enum drm_vmw_surface_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * @drm_vmw_surface_gb_v1: Corresponds to current gb surface format with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * svga3d surface flags split into 2, upper half and lower half.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) enum drm_vmw_surface_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) drm_vmw_gb_surface_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * struct drm_vmw_gb_surface_create_ext_req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * @base: Surface create parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * @version: Version of surface create ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * @svga3d_flags_upper_32_bits: Upper 32 bits of svga3d flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * @multisample_pattern: Multisampling pattern when msaa is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * @quality_level: Precision settings for each sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * @buffer_byte_stride: Buffer byte stride.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * @must_be_zero: Reserved for future usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * Input argument to the DRM_VMW_GB_SURFACE_CREATE_EXT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * Part of output argument for the DRM_VMW_GB_SURFACE_REF_EXT Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct drm_vmw_gb_surface_create_ext_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct drm_vmw_gb_surface_create_req base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) enum drm_vmw_surface_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) __u32 svga3d_flags_upper_32_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) __u32 multisample_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) __u32 quality_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) __u32 buffer_byte_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) __u32 must_be_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * union drm_vmw_gb_surface_create_ext_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * @req: Input argument as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * @rep: Output argument as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * Argument to the DRM_VMW_GB_SURFACE_CREATE_EXT ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) union drm_vmw_gb_surface_create_ext_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct drm_vmw_gb_surface_create_rep rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct drm_vmw_gb_surface_create_ext_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * DRM_VMW_GB_SURFACE_REF_EXT - Reference a host surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * Puts a reference on a host surface with a given handle, as previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * returned by the DRM_VMW_GB_SURFACE_CREATE_EXT ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * A reference will make sure the surface isn't destroyed while we hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * it and will allow the calling client to use the surface handle in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * the command stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * On successful return, the Ioctl returns the surface information given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * to and returned from the DRM_VMW_GB_SURFACE_CREATE_EXT ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * struct drm_vmw_gb_surface_ref_ext_rep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * @creq: The data used as input when the surface was created, as described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * above at "struct drm_vmw_gb_surface_create_ext_req"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * @crep: Additional data output when the surface was created, as described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * above at "struct drm_vmw_gb_surface_create_rep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * Output Argument to the DRM_VMW_GB_SURFACE_REF_EXT ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct drm_vmw_gb_surface_ref_ext_rep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct drm_vmw_gb_surface_create_ext_req creq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct drm_vmw_gb_surface_create_rep crep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * union drm_vmw_gb_surface_reference_ext_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * @req: Input data as described above at "struct drm_vmw_surface_arg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * @rep: Output data as described above at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * "struct drm_vmw_gb_surface_ref_ext_rep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * Argument to the DRM_VMW_GB_SURFACE_REF Ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) union drm_vmw_gb_surface_reference_ext_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct drm_vmw_gb_surface_ref_ext_rep rep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct drm_vmw_surface_arg req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * struct drm_vmw_msg_arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * @send: Pointer to user-space msg string (null terminated).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * @receive: Pointer to user-space receive buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * @send_only: Boolean whether this is only sending or receiving too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * Argument to the DRM_VMW_MSG ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct drm_vmw_msg_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) __u64 send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) __u64 receive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) __s32 send_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) __u32 receive_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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