^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2013 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef VIRTGPU_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIRTGPU_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Please note that modifications to all structs defined here are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * subject to backwards-compatibility constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * compatibility Keep fields aligned to their size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRM_VIRTGPU_MAP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRM_VIRTGPU_EXECBUFFER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRM_VIRTGPU_GETPARAM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRM_VIRTGPU_RESOURCE_CREATE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRM_VIRTGPU_RESOURCE_INFO 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRM_VIRTGPU_WAIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRM_VIRTGPU_GET_CAPS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VIRTGPU_EXECBUF_FLAGS (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) VIRTGPU_EXECBUF_FENCE_FD_IN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) VIRTGPU_EXECBUF_FENCE_FD_OUT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct drm_virtgpu_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __u64 offset; /* use for mmap system call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct drm_virtgpu_execbuffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __u64 command; /* void* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __u64 bo_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __u32 num_bo_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct drm_virtgpu_getparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __u64 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* NO_BO flags? NO resource flag? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* resource flag for y_0_top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct drm_virtgpu_resource_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u32 target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __u32 bind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __u32 depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __u32 array_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u32 last_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __u32 nr_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __u32 res_handle; /* returned by kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __u32 size; /* validate transfer in the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __u32 stride; /* validate transfer in the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct drm_virtgpu_resource_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __u32 res_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __u32 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct drm_virtgpu_3d_box {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __u32 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __u32 y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __u32 z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __u32 h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __u32 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct drm_virtgpu_3d_transfer_to_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __u32 bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct drm_virtgpu_3d_box box;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __u32 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct drm_virtgpu_3d_transfer_from_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __u32 bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct drm_virtgpu_3d_box box;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __u32 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct drm_virtgpu_3d_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __u32 handle; /* 0 is an invalid handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct drm_virtgpu_get_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __u32 cap_set_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __u32 cap_set_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRM_IOCTL_VIRTGPU_MAP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DRM_IOCTL_VIRTGPU_EXECBUFFER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct drm_virtgpu_execbuffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRM_IOCTL_VIRTGPU_GETPARAM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct drm_virtgpu_getparam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct drm_virtgpu_resource_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct drm_virtgpu_resource_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct drm_virtgpu_3d_transfer_from_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct drm_virtgpu_3d_transfer_to_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRM_IOCTL_VIRTGPU_WAIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct drm_virtgpu_3d_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRM_IOCTL_VIRTGPU_GET_CAPS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct drm_virtgpu_get_caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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