^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright © 2014-2018 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef _V3D_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define _V3D_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRM_V3D_SUBMIT_CL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRM_V3D_WAIT_BO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRM_V3D_CREATE_BO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRM_V3D_MMAP_BO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRM_V3D_GET_PARAM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRM_V3D_GET_BO_OFFSET 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRM_V3D_SUBMIT_TFU 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRM_V3D_SUBMIT_CSD 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * This asks the kernel to have the GPU execute an optional binner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * command list, and a render command list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * each CL executes. The VCD cache should be flushed (if necessary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * by the submitted CLs. The TLB writes are guaranteed to have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * flushed by the time the render done IRQ happens, which is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * trigger for out_sync. Any dirtying of cachelines by the job (only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * possible using TMU writes) must be flushed by the caller using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct drm_v3d_submit_cl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Pointer to the binner command list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * This is the first set of commands executed, which runs the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * coordinate shader to determine where primitives land on the screen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * then writes out the state updates and draw calls necessary per tile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * to the tile allocation BO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * This BCL will block on any previous BCL submitted on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * same FD, but not on any RCL or BCLs submitted by other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * clients -- that is left up to the submitter to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * using in_sync_bcl if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __u32 bcl_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /** End address of the BCL (first byte after the BCL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __u32 bcl_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Offset of the render command list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * This is the second set of commands executed, which will either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * execute the tiles that have been set up by the BCL, or a fixed set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * of tiles (in the case of RCL-only blits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * This RCL will block on this submit's BCL, and any previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * RCL submitted on the same FD, but not on any RCL or BCLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * submitted by other clients -- that is left up to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * submitter to control using in_sync_rcl if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __u32 rcl_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /** End address of the RCL (first byte after the RCL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 rcl_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /** An optional sync object to wait on before starting the BCL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __u32 in_sync_bcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /** An optional sync object to wait on before starting the RCL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __u32 in_sync_rcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /** An optional sync object to place the completion fence in. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __u32 out_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Offset of the tile alloc memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * This is optional on V3D 3.3 (where the CL can set the value) but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * required on V3D 4.1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __u32 qma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /** Size of the tile alloc memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __u32 qms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /** Offset of the tile state data array. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __u32 qts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Pointer to a u32 array of the BOs that are referenced by the job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __u64 bo_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Number of BO handles passed in (size is that times 4). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __u32 bo_handle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * struct drm_v3d_wait_bo - ioctl argument for waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * completion of the last DRM_V3D_SUBMIT_CL on a BO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * This is useful for cases where multiple processes might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * rendering to a BO and you want to wait for all rendering to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct drm_v3d_wait_bo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __u64 timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * There are currently no values for the flags argument, but it may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * used in a future extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct drm_v3d_create_bo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /** Returned GEM handle for the BO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Returned offset for the BO in the V3D address space. This offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * is private to the DRM fd and is valid for the lifetime of the GEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * This offset value will always be nonzero, since various HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * units treat 0 specially.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * This doesn't actually perform an mmap. Instead, it returns the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * offset you need to use in an mmap on the DRM device node. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * means that tools like valgrind end up knowing about the mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * There are currently no values for the flags argument, but it may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * used in a future extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct drm_v3d_mmap_bo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /** Handle for the object being mapped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /** offset into the drm node to use for subsequent mmap call. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum drm_v3d_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DRM_V3D_PARAM_V3D_UIFCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DRM_V3D_PARAM_V3D_HUB_IDENT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DRM_V3D_PARAM_V3D_HUB_IDENT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DRM_V3D_PARAM_V3D_HUB_IDENT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DRM_V3D_PARAM_V3D_CORE0_IDENT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DRM_V3D_PARAM_V3D_CORE0_IDENT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DRM_V3D_PARAM_V3D_CORE0_IDENT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DRM_V3D_PARAM_SUPPORTS_TFU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DRM_V3D_PARAM_SUPPORTS_CSD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct drm_v3d_get_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __u32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Returns the offset for the BO in the V3D address space for this DRM fd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * This is the same value returned by drm_v3d_create_bo, if that was called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * from this DRM fd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct drm_v3d_get_bo_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct drm_v3d_submit_tfu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __u32 icfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __u32 iia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __u32 iis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __u32 ica;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __u32 iua;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __u32 ioa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __u32 ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __u32 coef[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* First handle is the output BO, following are other inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * 0 for unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __u32 bo_handles[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* sync object to block on before running the TFU job. Each TFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * job will execute in the order submitted to its FD. Synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * against rendering jobs requires using sync objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __u32 in_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Sync object to signal when the TFU job is done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __u32 out_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Submits a compute shader for dispatch. This job will block on any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * previous compute shaders submitted on this fd, and any other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * synchronization must be performed with in_sync/out_sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct drm_v3d_submit_csd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __u32 cfg[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __u32 coef[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Pointer to a u32 array of the BOs that are referenced by the job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __u64 bo_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Number of BO handles passed in (size is that times 4). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __u32 bo_handle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* sync object to block on before running the CSD job. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * CSD job will execute in the order submitted to its FD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Synchronization against rendering/TFU jobs or CSD from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * other fds requires using sync objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __u32 in_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Sync object to signal when the CSD job is done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __u32 out_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif /* _V3D_DRM_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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